Stratix GX FPGA discontinued in June 13th, 2018


The Stratix® GX Device Handbook is composed of three volumes. Volume 1 is the Stratix GX FPGA family data sheet. Volume 2 provides detailed information on the device features, including the transceiver. Volume 3 contains information on configuration, remote system upgrades, and Stratix GX board design guidelines. To view all three volumes, click the link below.

Get more information on Stratix GX Pin-Outs.

Check the Knowledge Database for Known Issues with the Stratix GX Handbook.

Stratix GX Device Handbook (All Three Volumes) (21 MB)

Volume 1 (ver 1.2, Jun 2006, 3 MB)

Volume 2 (ver 2.0, Jun 2006, 10 MB)

Volume 3 (ver 1.2, Jun 2006, 5 MB)

Section I. Configuration & Remote System Upgrades

Section II. Design Guidelines

Section I. Stratix GX Transceiver User Guide

Section II. Clock Management

Section III. Memory

Section IV. I/O Standards

Section V. Digital Signal Processing

Section I. Stratix GX Transceiver User Guide

Following are the most frequently asked questions about Altera® Stratix GX devices.

What is the Stratix GX device family?

The Stratix GX device family is Altera's second-generation transceiver-based FPGA family, providing a low-risk path to applications requiring data transfer rates of up to 3.125 Gbps. Built on Altera's high-performance Stratix architecture, the Stratix GX device family supports the integration of high-bandwidth system-on-a-programmable-chip (SOPC) applications that once required the use of function-specific discrete transceiver devices.

Why is the Stratix GX device family significant?

The Stratix GX device family represents the integration of yet another major function into Altera's programmable SOPC solution. Many industries today are driven by the need for high speed across all design segments. With Stratix GX devices, customers receive a complete system design platform. In addition to the silicon's integrated 3.125-Gbps transceiver technology and high-performance Stratix device architecture, Altera offers the powerful Quartus® II design software, hard and soft intellectual property (IP), and all the peripherals and support infrastructure needed to get high-speed systems up and running.

Which applications does the Stratix GX device family address?

The Stratix GX device family can be used in a wide range of applications including mass storage systems, high-end consumer electronics, and high-speed communications. Designed with up to 20 channels, each operating at up to 3.125 Gbps, the Stratix GX device family is well equipped to handle high-bandwidth applications that include switch fabrics and I/O protocol bridging.

In what way is the Stratix GX family low risk?

Board-level design for multi-gigabit transceivers is a complex and challenging task, independent of the transceiver technology involved. Managing the signal integrity issues and ensuring a successful implementation requires close attention to detail, access to the necessary design tools, and the confidence that the silicon will perform as advertised.

With Stratix GX devices, Altera provides not only robust, silicon that works to specifications, but also the software tools, intellectual property, support infrastructure, documentation, board design guidelines, product interoperability testing, and development kits needed to ensure that designers have everything they need to develop working, transceiver-based systems. Leveraging experience gained with the Mercury transceiver-based product family as well as years of high-speed digital design with previous generation products, Altera designed Stratix GX devices with close attention to the details commonly faced by designers of multi-gigabit systems.

In addition, the inherent flexibility of FPGAs gives designers the ability to complete full design iterations in a short amount of time. This means that they can quickly implement last minute modifications — for anything from changes to interface protocol specifications to the addition of new functionality — without a significant impact on product delivery.

How are Stratix GX devices different from Stratix devices?

Offering significant performance increases over previous generation architectures and unrivaled logic and memory density, the Stratix device architecture provides the basis upon which Stratix GX devices are built. All of the same innovative features, including TriMatrix memory, digital signal processing (DSP) blocks, Terminator technology, and dedicated external memory interface circuitry are available in Stratix GX devices. Two key new features differentiate Stratix GX devices from Stratix devices:

  • Gigabit transceiver blocks
  • Dynamic phase alignment (DPA) blocks

More information is available about the differences between Stratix and Stratix GX devices at

What are gigabit transceiver blocks?

Stratix GX gigabit transceiver blocks are embedded transceiver blocks that feature four full-duplex channels capable of transmission speeds up to 3.125 Gbps using clock data recovery (CDR). Each channel features dedicated circuitry that implements various stages of the data recovery/transmission, serialization/deserialization, decoding/encoding, and synchronization processes. A seamless interface with the programmable logic fabric ensures reliable data transfer, maximized data throughput, and simplified timing analysis.

What is dynamic phase alignment?

The dynamic phase alignment (DPA) feature in Stratix GX devices repeatedly compares incoming data on a channel-by-channel basis with an incoming system clock. Essential to many emerging high-speed interface protocols, DPA removes channel-to-channel and clock-to-channel timing variations introduced by unmatched board trace lengths, jitter, and other skew-inducing effects.

Why is DPA important?

Recognizing the challenges that system architects face in designing high-speed, source-synchronous data transfer applications, Altera designed the Stratix GX device family with embedded DPA functionality to dramatically simplify printed circuit board design. DPA eliminates signal issues introduced by skew-inducing effects. Emerging bus transfer protocols such as SPI-4.2 require DPA, and the added board-level reliability allow Stratix GX source-synchronous signals with DPA to reach data rates as high as 1 Gbps.

What are the benefits of hard DPA as compared to soft DPA?

By incorporating the DPA feature directly into embedded silicon on the source-synchronous channels, Stratix GX devices provide a verified, reliable solution to the need for skew reduction and higher speed transmission. A soft DPA implementation, in addition to consuming valuable logic resources, can rapidly consume global clocks and PLLs in the device and can be susceptible to errors when faced with temperature and voltage changes. The Stratix GX hard DPA implementation avoids these issues and ensures errorless data transmission.

Are the Stratix GX devices interoperable with ASSP devices?

By supporting a wide range of high-speed interface protocols, the Stratix GX device family has the ability to interoperate with ASSPs over a backplane or directly from chip to chip. This allows Stratix GX devices to be seamlessly introduced into systems with existing transceiver ASSPs and to effectively implement bridging functions between otherwise incompatible products.

Which high-speed interfaces does the Stratix GX device family support?

The Stratix GX device family supports numerous emerging interface protocols. This includes interfaces that require CDR functionality such as 10 Gigabit Ethernet XAUI, Gigabit Ethernet, InfiniBand, and SONET/SDH as well as interfaces that use source-synchronous signaling techniques such as SPI-4.2, HyperTransport, and 10 Gigabit Ethernet XSBI.

Table 1 shows the interface standards that the Stratix GX devices support.

Table 1: Stratix GX Interface Support

Interface Interface Type Clocking Scheme Data Rate
SONETSerialCDR2.488 Gbps
10 Gigabit Ethernet XAUI (1)SerialCDR3.125 Gbps
Gigabit EthernetSerialCDR1.25 Gbps
InfiniBandSerialCDR2.5 Gbps
Serial RapidIOSerialCDR1.25, 2.5, or 3.125 Gbps
Fibre ChannelSerialCDR1.0625 or 2.125 Gbps
PCI ExpressSerialCDR2.5 Gbps
SMPTE 292MSerialCDR1.485 Gbps
SPI-4 Phase 2ParallelSource-Synchronous1 Gbps
HyperTransportParallelSource-Synchronous800 Mbps
Parallel RapidIOParallelSource-Synchronous1 Gbps
CSIX StreamingParallelSource-Synchronous1 Gbps
10 Gigabit Ethernet XSBI (2)ParallelSource-Synchronous844 Mbps


(1) 10 gigabit attachment unit interface
(2) 10 gigabit sixteen-bit interface

How does the Stratix GX device family relate to the Mercury device family?

The Stratix GX device family features significant enhancements in capabilities, performance, and density over the Mercury device family. As the first FPGA to incorporate transceiver technology, the Mercury device family supports data transfer rates up to 1.25 Gbps. With the Quartus II version 2.1 design software, Mercury designs can be re-targeted or configured to operate with a Stratix GX device. With the Mercury devices, Altera gained invaluable experience on supporting customers designing multi-gigabit applications.

What are the members of the Stratix GX device family?

The Stratix GX device family consists of seven device family members that range in density from 10,570 to 41,250 logic elements (LEs). Devices are available with up to 20 transceiver channels. Table 2 gives an overview of the Stratix GX devices.

Table 2: Stratix GX Device Overview

Device Logic Elements Gigabit Transceiver Blocks Full-Duplex Transceiver Channels Full-Duplex Source-Synchronous Channels SpeedGrades (1) Packages
EP1SGX10C10,5701422-5, -6, -7 (2)672-Pin FBGA (3)
EP1SGX10D10,5702822-5, -6, -7672-Pin FBGA
EP1SGX25C25,6601439-5, -6, -7672-Pin FBGA
EP1SGX25D25,6602839-5, -6, -7672-Pin FBGA
1,020-Pin FBGA
EP1SGX25F25,66041639-5, -6, -71,020-Pin FBGA
EP1SGX40D41,2502845-5, -6, -71,020-Pin FBGA
EP1SGX40G41,25052045-5, -6, -71,020-Pin FBGA


(1) -5 represents fastest speed grade
(2) -5 and -6 devices support 3.125-Gbps performance, -7 devices support 2.5-Gbps performance
(3) FineLine BGA® package

When will the Stratix GX devices be available?

The EP1SGX25F device will be available in Q1 2003. EP1SG40 devices will follow soon after in Q2 2003. All family members will be shipping by the middle of 2003.

What is the process technology for the Stratix GX device family?

The Stratix GX device family is Altera's fourth product based on TSMC's advanced 1.5-V, 0.13-µm, all-layer-copper process technology. Exercised first with the APEX II EP2A70 devices and continuing on through the entire Stratix and Cyclone device families, both Altera and TSMC have gained valuable experience in producing devices at this process geometry.

What is the volume price for the Stratix GX device family?

Volume pricing will start at $99 for the EP1SGX10C in 50,000 unit volumes in mid-2004.

How does the Stratix GX device family pricing compare to the Stratix devices?

Production volume pricing for Stratix GX devices is slightly higher than Stratix devices with equivalent logic and memory density. The difference is expected to be competitive with the cost of a discrete transceiver implementation, while providing the significant benefits of integration.

What software is available to support the Stratix GX device family?

The Stratix GX device family is fully supported by the Quartus II version 2.1 design software. In addition to Stratix GX compilation support, the Quartus II version 2.1 software offers a host of new features, including advanced timing closure capabilities, the SignalTap® II logic analyzer, and formal verification support.

Which IP cores will be available for the Stratix GX device family?

All IP cores currently available for the Stratix devices will be available for the Stratix GX device family.

New IP cores for implementing I/O protocols using the embedded gigabit transceiver blocks and DPA are available from Altera and Altera Megafunction Partner Program (AMPPSM) partners including

  • 10 Gigabit Ethernet Media Access Controller (MAC)
  • 10 Gigabit Ethernet Physical Coding Sub-layer (PCS)
  • 1 Gigabit Ethernet MAC
  • SONET framer
  • Serial RapidIO
  • Parallel RapidIO with DPA
  • POS-PHY Level 4 with DPA

Transceiver-based IP cores leverage the dedicated functional blocks within each gigabit transceiver channel for an easy-to-use solution for complex multi-gigabit applications. Additional functionality and higher-level processing is implemented in the general programmable logic resources in the device.

Does the Stratix GX device family support the Nios® embedded processor?

Version 2.1 of the Nios embedded processor is fully supported by the Stratix GX device family. When targeted for a Stratix GX device, the Nios embedded processor takes full advantage of the TriMatrix on-chip memory, high-performance interconnects, and embedded DSP blocks available within the device.

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