Following are the most frequently asked questions about Altera® Stratix™ GX devices.
What is the Stratix GX device family?
The Stratix GX device family is Altera's second-generation transceiver-based FPGA family, providing a low-risk path to applications requiring data transfer rates of up to 3.125 Gbps. Built on Altera's high-performance Stratix architecture, the Stratix GX device family supports the integration of high-bandwidth system-on-a-programmable-chip (SOPC) applications that once required the use of function-specific discrete transceiver devices.
Why is the Stratix GX device family significant?
The Stratix GX device family represents the integration of yet another major function into Altera's programmable SOPC solution. Many industries today are driven by the need for high speed across all design segments. With Stratix GX devices, customers receive a complete system design platform. In addition to the silicon's integrated 3.125-Gbps transceiver technology and high-performance Stratix device architecture, Altera offers the powerful Quartus® II design software, hard and soft intellectual property (IP), and all the peripherals and support infrastructure needed to get high-speed systems up and running.
Which applications does the Stratix GX device family address?
The Stratix GX device family can be used in a wide range of applications including mass storage systems, high-end consumer electronics, and high-speed communications. Designed with up to 20 channels, each operating at up to 3.125 Gbps, the Stratix GX device family is well equipped to handle high-bandwidth applications that include switch fabrics and I/O protocol bridging.
In what way is the Stratix GX family low risk?
Board-level design for multi-gigabit transceivers is a complex and challenging task, independent of the transceiver technology involved. Managing the signal integrity issues and ensuring a successful implementation requires close attention to detail, access to the necessary design tools, and the confidence that the silicon will perform as advertised.
With Stratix GX devices, Altera provides not only robust, silicon that works to specifications, but also the software tools, intellectual property, support infrastructure, documentation, board design guidelines, product interoperability testing, and development kits needed to ensure that designers have everything they need to develop working, transceiver-based systems. Leveraging experience gained with the Mercury transceiver-based product family as well as years of high-speed digital design with previous generation products, Altera designed Stratix GX devices with close attention to the details commonly faced by designers of multi-gigabit systems.
In addition, the inherent flexibility of FPGAs gives designers the ability to complete full design iterations in a short amount of time. This means that they can quickly implement last minute modifications — for anything from changes to interface protocol specifications to the addition of new functionality — without a significant impact on product delivery.
How are Stratix GX devices different from Stratix devices?
Offering significant performance increases over previous generation architectures and unrivaled logic and memory density, the Stratix device architecture provides the basis upon which Stratix GX devices are built. All of the same innovative features, including TriMatrix™ memory, digital signal processing (DSP) blocks, Terminator™ technology, and dedicated external memory interface circuitry are available in Stratix GX devices. Two key new features differentiate Stratix GX devices from Stratix devices:
Gigabit transceiver blocks
Dynamic phase alignment (DPA) blocks
More information is available about the differences between Stratix and Stratix GX devices at www.altera.com/products/devices/stratixgx/features/sgx-stratixgx_stratix.html.
What are gigabit transceiver blocks?
Stratix GX gigabit transceiver blocks are embedded transceiver blocks that feature four full-duplex channels capable of transmission speeds up to 3.125 Gbps using clock data recovery (CDR). Each channel features dedicated circuitry that implements various stages of the data recovery/transmission, serialization/deserialization, decoding/encoding, and synchronization processes. A seamless interface with the programmable logic fabric ensures reliable data transfer, maximized data throughput, and simplified timing analysis.
What is dynamic phase alignment?
The dynamic phase alignment (DPA) feature in Stratix GX devices repeatedly compares incoming data on a channel-by-channel basis with an incoming system clock. Essential to many emerging high-speed interface protocols, DPA removes channel-to-channel and clock-to-channel timing variations introduced by unmatched board trace lengths, jitter, and other skew-inducing effects.
Why is DPA important?
Recognizing the challenges that system architects face in designing high-speed, source-synchronous data transfer applications, Altera designed the Stratix GX device family with embedded DPA functionality to dramatically simplify printed circuit board design. DPA eliminates signal issues introduced by skew-inducing effects. Emerging bus transfer protocols such as SPI-4.2 require DPA, and the added board-level reliability allow Stratix GX source-synchronous signals with DPA to reach data rates as high as 1 Gbps.
What are the benefits of hard DPA as compared to soft DPA?
By incorporating the DPA feature directly into embedded silicon on the source-synchronous channels, Stratix GX devices provide a verified, reliable solution to the need for skew reduction and higher speed transmission. A soft DPA implementation, in addition to consuming valuable logic resources, can rapidly consume global clocks and PLLs in the device and can be susceptible to errors when faced with temperature and voltage changes. The Stratix GX hard DPA implementation avoids these issues and ensures errorless data transmission.
Are the Stratix GX devices interoperable with ASSP devices?
By supporting a wide range of high-speed interface protocols, the Stratix GX device family has the ability to interoperate with ASSPs over a backplane or directly from chip to chip. This allows Stratix GX devices to be seamlessly introduced into systems with existing transceiver ASSPs and to effectively implement bridging functions between otherwise incompatible products.
Which high-speed interfaces does the Stratix GX device family support?
The Stratix GX device family supports numerous emerging interface protocols. This includes interfaces that require CDR functionality such as 10 Gigabit Ethernet XAUI, Gigabit Ethernet, InfiniBand, and SONET/SDH as well as interfaces that use source-synchronous signaling techniques such as SPI-4.2, HyperTransport, and 10 Gigabit Ethernet XSBI.
Table 1 shows the interface standards that the Stratix GX devices support.