The Stratix® II GX Device Handbook is comprised of two volumes. Volume 1 is the Stratix II GX FPGA family data sheet. Volume 2 includes the Stratix II GX Transceiver User Guide. Volume 2 also provides detailed information on Stratix II GX features and PCB layout guidelines. To view both volumes, click the link below.

Get more information on Stratix II GX Pin-Outs.

Get more information on pin connection guidelines.

Stratix II GX Device Handbook (Complete Two-Volume Set) (14 MB)

Volume 1 (ver 4.4, Jun 2009, 4 MB)

Volume 2 (ver 4.3, Oct 2007, 15 MB)

Section I. Stratix II GX Transceiver User Guide

Section II. Clock Management

Section III. Memory

Section IV. I/O Standards

Section V. Digital Signal Processing (DSP)

Section VI. Configuration & Remote System Upgrades

Section VII. PCB Layout Guidelines

Following are the most frequently asked questions about Stratix® II GX devices.

What are Stratix II GX FPGAs?

The 90-nm Stratix II GX FPGAs are Intel's third generation of FPGAs with embedded transceivers. The devices are part of a complete programmable solution from Altera aimed at the growing number of applications and protocols requiring high-speed serial interconnect. Stratix II GX devices share the same ground-breaking architecture as Intel's high-density Stratix II FPGAs and integrate up to 20 serializer/deserializer (SERDES)-based transceivers.

The Stratix II GX serial transceivers operate from 600 Mbps to 6.375 Gbps and feature low jitter generation and high jitter tolerance. Added features, including transmit pre-emphasis, receive equalization, and programmable differential output voltage (VOD) provide a low bit-error rate (BER) solution for even the most challenging backplanes. These new devices with embedded transceivers support many protocol standards, including PCI Express, serial digital interface (SDI), XAUI, SONET, Gigabit Ethernet, SerialLite II, Serial RapidIO™ (SRIO), and Common Electrical Interface 6 Gbps (CEI-6G) Long Reach and Short Reach standards. The Stratix II GX device transceivers consume only 140 mW per channel at 3.125 Gbps and 225 mW per channel at 6.375 Gbps. This is the lowest power consumption of any FPGA with integrated transceivers.

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What are the benefits of using Stratix II GX devices?

Intel developed Stratix II GX devices based on customer input and protocol roadmaps. Stratix II GX FPGAs and their complete system solution of intellectual property (IP), system models, reference designs, signal integrity tools, and supporting collateral help customers complete their designs quickly and efficiently. Additionally, the transceivers have been designed to provide excellent signal integrity and the lowest-power solution in an FPGA, resulting in a reduction in board layout risks and improved system performance margins.

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What are transceiver blocks?

Stratix II GX transceivers are full-duplex, high-speed, serial I/O channels capable of transmission speeds up to 6.375 Gbps using clock data recovery (CDR). Each transceiver features dedicated circuitry that implements various stages of the data recovery/transmission, SERDES, encoding/decoding, and synchronization processes. A seamless interface with the programmable logic fabric ensures reliable data transfer, maximized data throughput, and simplified timing analysis.

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What new key transceiver features are offered in Stratix II GX devices?

Intel introduces a suite of new transceiver features with Stratix II GX FPGAs that expand the capabilities of FPGAs in high-performance applications. The following table describes the feature differences between Stratix II GX and Stratix GX devices.

Table 1. Stratix II GX & Stratix GX Transceiver Features

Parameter Stratix II GX Stratix GX
Data Rate Range600 Mbps – 6.375 Gbps500 Mbps – 3.1875 Gbps
Minimum Data Rate with Oversampling270 Mbps270 Mbps
Power Consumption
  • 140 mW per channel at 3.1875 Gbps
  • 225 mW per channel at 6.375 Gbps
  • 150 mW per channel at 3.1875 Gbps
Maximum Pre-Emphasis Level
  • 500%
  • 3 taps
  • 140%
  • 2 taps
Maximum Equalization Level
  • 17 dB
  • 4 stages
  • 9 dB
  • 1 stage
Output Differential Voltage Range400 mV – 1,400 mV400 mV – 1,600 mV
Channel Groups
  • Quad (4 receive PLLs (1), 2 Transmit PLLs)
  • Independent channels
  • 4 different data rates
  • Quad (4 receive PLLs, 1 transmit PLL)
  • Independent channels
  • 1 data rate
Dynamic ReconfigurationYesYes

Notes to Table 1:

  1. PLLs: Phase-locked loops

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Which applications do the Stratix II GX devices address?

The Stratix II GX devices can be used in a wide range of applications including mass storage systems, high-end consumer electronics, and high-speed communications. Designed with up to 20 channels—each operating at up to 6.375 Gbps—Stratix II GX devices are well equipped to handle high-bandwidth applications that include switch fabrics and I/O protocol bridging.

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Which protocols are supported by the Stratix II GX devices and how are they supported?

Stratix II GX devices provide protocol support in various layers. For information on the hard IP in the physical coding sublayer (PCS) blocks of Stratix II GX devices, see Table 2, below. For examples of Intel's protocol solutions, including soft IP, boards, reference designs, and documentation, see Table 3.

Table 2. Built-In Protocol Standards Support

(Data Rate)
PCI Express
(2.5 Gbps)
PIPE-compliant PCS block
(6.375 Gbps)
8B/10B encoder/decoder
Gigabit Ethernet
(1.25 Gbps)
Gigabit Ethernet state machine
(3.125 Gbps)
XAUI state machine
SRIO standard
(1.25, 2.5 & 3.125 Gbps)
8B/10B encoder/decoder
(622 Mbps)
A1A2 pattern detector and aligner
(2.488 Gbps)
A1A2 or A1A1A2A2 pattern detector and aligner
Standard-definition SDI (SD‑SDI)
(270 Mbps)
Pattern detector
High-definition SDI (HD-SDI)
(1.4835 Gbps or 1.485 Gbps)
Pattern detector
SerialLite II
622 Mbps – 6.375 Gbps
8B/10B encoder/decoder

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How do Stratix II GX devices help reduce PCB design risk?

Board-level design for transceivers is a complex and challenging task, independent of the transceiver technology involved. Managing the signal integrity issues and ensuring a successful implementation requires close attention to detail, access to the necessary design tools, and the confidence that the silicon will perform as advertised.

Stratix GX FPGAs are widely recognized for their signal integrity. Stratix II GX FPGAs build on this technology to provide a robust low-jitter solution that includes a number of features to improve signal integrity. Stratix II GX devices offer high levels of pre-emphasis and equalization enabling the transceiver to operate at 6.375 Gbps across a backplane.

Stratix II GX devices are also delivered with a number of tools and collateral to support board simulation and PCB design. This includes SPICE simulation models and third-party PCB design kits ready for use with industry PBC design tools. These all help ensure the PCB is correct the first time.

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Why are the Stratix II GX devices targeted at 6.375 Gbps and not 10 Gbps?

The sweet spot of today’s protocol requirement ranges from 1.0 Gbps to 5.0 Gbps for single-channel transceivers. Over the next three years this range will change to 3.125 Gbps to 6.375 Gbps. While there will be limited applications that require higher transceiver speeds, the cost to implement 10 Gbps performance is high. Support for 10 Gbps results in die-size, power, and signal integrity penalties; the penalties are very significant because few customers actually require the 10-Gbps speed. For example, a 20-port, 6.375-Gbps implementation in Stratix II GX FPGAs dissipates 4.5 watts, versus a competing solution that dissipates 11 watts at the same data rate, resulting in a power penalty. Intel provides substantial support for the key protocols and performance metrics that will be required for the majority of customers over the next three years.

The few applications requiring 10 Gbps need only a small number of these high-speed transceivers; Stratix II GX FPGAs work efficiently with external transceivers to address this requirement without placing overhead on the transceivers in each device.

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Why is transceiver power consumption important?

A Stratix II GX transceiver consumes around 1/3 of the power of its nearest competitor, typically a savings of 350 mW per channel. At first this may seem insignificant when compared to the FPGA fabric, but in reality it is significant. For example, if you are using 20 channels, it can add around 7 W of power. Generally, transceivers are used in areas where cooling is difficult: close to backplanes, or in areas of a system without fans. It is therefore important to keep the power requirement low.

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What is the Intel “complete solution” offering?

Transceiver design is often seen as complex, particularly when paired with achieving protocol compliance. Stratix II GX FPGAs are provided as a complete solution aimed at removing the complexity from transceiver designs and reducing the design effort required for protocol compliance. This allows you to concentrate on your core competency and get to market quickly.

The complete solution includes IP, reference designs, development boards aimed at specific protocols, evaluation boards aimed at signal Integrity, documentation, and characterization reports. Characterization is performed by protocol, making compliance testing simpler. The solution also includes signal integrity tools and device models for board layout and simulation.

Table 3. Examples of Intel's FPGA Serial Protocol Solutions

Standard Complete Protocol Solutions
PCI Express
  • PCI Express Intel FPGA IP functions
    • PCI-SIG* compliant,
    • Supports x1, x4, and x8 endpoint
  • Development kit with x8 edge connector and slot, schematics, and layout
  • Characterization report
  • Reference design
Gigabit Ethernet
  • Gigabit Ethernet media access control (MAC) IP
  • Development kit with HSSDC2 high-speed connector, schematics, and layout
  • Characterization report
  • 10 Gigabit Ethernet MAC IP from MorethanIP
  • Development kit with schematics and layout
  • Characterization report
  • SDI IP
    • Full-duplex interface that supports rate detection, cyclic redundancy check (CRC), and video pattern generator
  • Development kit with driver, cable equalizer, schematics, and layout
  • Characterization report

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Why would I use SerialLite II?

Many protocols now exist to facilitate serial data transmission. They are often used in applications that require a high degree of functionality and integration supporting both lower and upper layers of the protocol stack. In turn, this leads to the use of a large amount of FPGA logic to fully support the protocol. Often, for example in chip-to-chip or proprietary applications, it is not necessary to use all the features of a fully functional protocol and many applications only require the link layer of the protocol. In these applications, customers are paying a design penalty to incur the extra logic for features not being used.

SerialLite II is a link-layer protocol aimed at addressing the needs of customers requiring a simple protocol to address their application. SerialLite II is an open-standard protocol, but is provided by Altera as a standard IP block. The core is scaleable and be can be tailored to meet the your interfacing needs without adding unnecessary architecture.

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How are Stratix II GX devices different from Stratix II devices?

Stratix II devices are the industry's largest and fastest 90-nm FPGAs. They offer significant performance increases over previous-generation architectures and unrivalled logic and memory density. The Stratix II device architecture provides the basis upon which Stratix II GX devices are built. All of the same innovative features, including TriMatrix memory, digital signal processing (DSP) blocks, Terminator technology, 1-Gbps source-synchronous I/Os using dynamic phase alignment (DPA), and dedicated external memory interface circuitry are available in Stratix GX II devices.

Stratix II GX devices integrate up to 20 transceivers onto the Stratix II FPGA architecture. The transceivers, which operate between 600 Mbps and 6.375 Gbps, provide a robust solution for high-speed-I/O-based applications and protocols.

Additional information is available on the Altera website about the differences between Stratix II and Stratix II GX devices.

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Are Stratix II GX devices interoperable with ASSP devices?

By supporting a wide range of high-speed interface protocols, Stratix II GX devices have the ability to interoperate with ASSPs over a backplane or directly from chip to chip. This allows Stratix II GX devices to be seamlessly introduced into systems with existing transceiver ASSPs and to effectively implement bridging functions between otherwise incompatible products.

Are Stratix II GX devices interoperable with Stratix GX devices?

The transceiver buffers within Stratix GX and Stratix II GX devices are both extremely flexible and offer a number of features to overcome issues with signal integrity. It is relatively simple to use Stratix II GX and Stratix GX transceivers within the same system and allow them to interoperate.

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Which high-speed interfaces do the Stratix II GX devices support?

The Stratix II GX devices support numerous emerging interface protocols. This includes interfaces that require CDR functionality such as PCI Express, Gigabit Ethernet, SONET/synchronous digital hierarchy (SONET/SDH), XAUI, SD-SDI and HD-SDI, CEI-6G, the SRIO standard, and the Altera SerialLite II protocol. Table 4 shows the interface standards that the Stratix II GX devices support and the complete solution offered by Altera.

Table 4. Interface Standards

Standards Data Rate Complete Solution
IP Development Kit Characterization Cookbook (1)
Protocol Specific Standard
PCI-Express 1.12.5 GbpsYesYes-YesYes
CEI-6G6.25 Gbps--YesYesYes
SDH / SONET OC-12622 MbpsYes-YesYesYes
SDH / SONET OC-482.488 GbpsYes-YesYesYes
Gigabit Ethernet1.25 GbpsYes-YesYesYes
XAUI3.125 GbpsYes-YesYesYes
SD-SDI270 MbpsYesYes-YesYes
HD-SDI1.488 GbpsYesYes-YesYes
SRIO Standard1.25, 2.5, 3.125 GbpsYes-YesYesYes
SerialLite II622 Mbps – 6.375 GbpsYes-YesYesYes

Notes to Table 4:

  1. The cookbook provides complete documentation on how to implement the protocol.

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What are the individual Stratix II GX devices?

There are eight different Stratix II GX devices that range in density from 33,880 to 132,540 equivalent logic elements (LEs). Devices are available with up to 20 transceiver channels. Table 5 gives an overview of Stratix II GX device features. Table 6 provides details on device packaging.

Table 5. Stratix II GX Device Features (1)

Feature Device
Transceiver Data Rate600 Mbps – 6.375 Gbps
Adaptive Logic Modules (ALMs) (2)13,55224,17636,38453,016
Equivalent LEs (2)33,88060,44090,960132,540
LVDS Channels29294578
M512 RAM Blocks202329488699
M4K RAM Blocks144255408609
MRAM Blocks1246
Total RAM Bits1,369,7282,544,1924,520,4486,747,840
DSP Blocks16364863
Embedded Multipliers (3)64144192252
PLLs (4)4888

Notes to Table 5:

  1. Features are preliminary and subject to change.
  2. Each ALM is equivalent to 2.5 LEs.
  3. Each DSP block in a Stratix II GX device can implement four 18×18 multipliers or one 36×36 multiplier. To obtain the total number of 36×36 multipliers per device, divide the total number of 18×18 multipliers by a factor of 4.
  4. Includes both enhanced PLLs and fast PLLs.

Table 6. Stratix II GX Transceiver Channels, Device Package and Maximum User I/O Pins (1, 2)

LVDS Channels Device Package and User I/O
Device Transceiver Channels Receive Transmit F780 (29 mm) User I/O Pins F1152 (35 mm) User I/O Pins F1508 (40 mm) User I/O Pins
EP2SGX60E1242 (3)42-534-
EP2SGX90E1247 (3)45-558-
EP2SGX90F1659 (3)59--650
EP2SGX130G2073 (3)71--734

Notes to Table 6:

  1. The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock-reference pins for high-speed I/O capability.
  2. User I/O counts are preliminary and subject to change.
  3. Includes two differential clock inputs that can also be used for two additional channels for the differential receiver.

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What are the key features included in the Stratix II GX FPGA fabric?

Table 7. Stratix II GX Device Features (1)

Technology & Features Stratix II GX FPGAs
Process Technology90 nm
Logic StructureALM: Enhanced look-up table (LUT)-based structure with support for functions of up to 7 inputs
Logic DensityUp to 132,540 equivalent LEs
TriMatrix MemoryUp to 6.7 Mbits of embedded memory
External Memory Interface SupportDDR2, RLDRAM II, QDRII, DDR, SDR SDRAM
DSP BlocksUp to 252 18x18 multipliers
Enhanced & Fast PLLsUp to 4 enhanced and 8 fast PLLs
Global Clock NetworksUp to 16 global clock networks
Source-Synchronous SignalingUp to 1-Gbps data rates for LVDS and HyperTransport technology
Source-Synchronous Protocol SupportPCI Express, CEI-6G, SDI, XAUI, SONET, SRIO, Gigabit Ethernet, and SerialLite II
Single-Ended I/O SupportSSTL-2 (I & II), SSTL-18 (I & II), 1.8-V HSTL (I & II), 1.5-V HSTL (I & II), 3.3-V PCI, 3.3-V PCI-X 1.0, 3.3-V/2.5-V/1.8-V LVTTL, 3.3‑V/2.5‑V/1.8‑V/1.5‑V LVCMOS
Design SecurityAdvanced encryption standard (AES) algorithm with
128-bit key
On-Chip TerminationSeries and differential
Nios II Processor SupportYes

Notes to Table 7:

  1. These features are also found in Stratix II FPGAs.

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Which external memory interfaces do Stratix II GX FPGAs support?

Stratix II GX FPGAs meet the performance requirements of the latest SRAM and DRAM devices, as shown below. External memory devices can be easily connected to Stratix II GX FPGAs to provide additional storage capacity outside of the abundant on-chip memory resources without causing performance bottlenecks. You can purchase Altera- or third-party-developed IP memory controller cores, download royalty-free reference designs from the Altera website, or develop your own customized cores for your specific applications.

Table 8. High-Performance External Memory Interface Support in Stratix II GX Devices

Memory Technology I/O Standard Bus Width Maximum Clock Speed
DDR SDRAMSSTL-2 Class I & II72 bits200 MHz
DDR2 SDRAMSSTL-18 Class I & II72 bits267 MHz
RLDRAM IISSTL-2 Class I & II36 bits300 MHz
QDR SRAMHSTL-18 Class I & II36 bits167 MHz
QDRII SRAMHSTL-18 Class I & II36 bits250 MHz

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What speed grades will be available?

Stratix II GX devices will be available in three speed grades: -3, -4, and -5, with -3 being the fastest and -5 the slowest.

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What is the remote system upgrade feature?

The remote system upgrade feature allows you to reconfigure Stratix II GX devices from a remote source, extending your product’s lifespan while also saving time and costs. New configuration data can be sent to a system from a remote source, saved to an external memory device such as an advanced configuration device, and subsequently used to reconfigure the Stratix II GX device. If an error occurs during this process, the devices automatically initiate re-configuration from the external memory device using safe, default factory-configured settings.

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What is the design security feature in Stratix II GX FPGAs?

Stratix II GX devices use the advanced encryption standard (AES) algorithm with a 128-bit key to encrypt the configuration bitstream. Selected by the National Institute of Standards and Technology (NIST) and adopted by the United States government to protect sensitive information, AES is the most advanced encryption algorithm available today. Other FPGA vendors support triple data encryption standard (triple DES) bitstream encryption using a battery to power-up or back-up the volatile key. Such approaches are very difficult to implement, increasing board-level concerns regarding possible system malfunctions and the need for redundancy. When the battery fails in the field, for example, the FPGA will not power on, causing the board to malfunction. Stratix II GX devices simplify system design by eliminating the need for a constant power source. Stratix II GX devices support the best configuration bit stream encryption available in the FPGA market.

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When did Stratix II GX devices become available?

Engineering samples of the first Stratix II GX device, the EP2S90GX, were made available in Q1 2006, and the remaining Stratix II GX devices rolled out over the following six months.

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What is the process technology for Stratix II GX devices?

Stratix II GX devices are based on the 1.2-V, 90-nm, nine-layer-metal, all-layer-copper process technology from TSMC. This extends the process-leadership advantages Intel gained when rolling out the Stratix II and Cyclone® II families, now in production. Stratix II GX devices use a low-k dielectric and are manufactured on 300-mm wafers.

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What is the volume price for Stratix II GX devices?

Pricing for Stratix II GX devices is dependent on the density, package, performance, and volume quantities of the devices ordered. Typically, Stratix II GX pricing will be lower than using the equivalent Stratix II device with an external transceiver. Please contact your local Intel sales representative or distributor for more specific pricing information.

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Why did Intel announce Stratix II GX FPGAs before silicon was ready?

Altera customers have stated they prefer to start high-density FPGA software design before they have the actual devices. Advanced knowledge of the features and functions of the Stratix II GX devices allowed system architects and designers to begin implementing the transceiver as well as the logic functionality of their next-generation systems. Designers were also able to start developing their Stratix II GX FPGA designs using HSPICE simulation models, optimized Stratix II GX device IP functions (such as PCI Express and SerialLite II) and the Quartus® II development software version 5.1 right away.

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What software is available to support Stratix II GX devices?

Stratix II GX devices are fully supported by Quartus II design software version 5.1 and beyond. In addition to Stratix II GX device compilation support, Quartus II version 5.1 software offers a host of new features, including advanced timing closure capabilities, the Signal Tap logic analyzer, and formal verification support.

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Which third-party tools will support Stratix II GX devices?

In addition to the Quartus II integrated synthesis tool, synthesis and simulation tools from leading EDA vendors Cadence, Mentor Graphics, Synopsys, and Synplicity all support Stratix II GX devices, ensuring the highest quality of results in Intel FPGAs.

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Which IP cores will be available for Stratix II GX devices?

All IP cores currently available for Stratix II FPGAs will be available for Stratix II GX devices.

New IP cores for implementing I/O protocols using the embedded transceiver blocks are available from Intel and Intel FPGA IP partners including:

  • PCI Express
  • 10 Gigabit Ethernet Media MAC
  • 10 Gigabit Ethernet PCS
  • 1 Gigabit Ethernet MAC
  • SONET Framer
  • SerialLite II

Transceiver-based IP cores leverage the dedicated functional blocks within each transceiver channel for an easy-to-use solution for complex applications. Additional functionality and higher-level processing are implemented in the general programmable logic resources within the device.

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Can Nios II embedded processors be used with Stratix II GX devices?

Yes, the advanced architectural features of Stratix II GX devices combined with the Nios II family of embedded processors offer unparalleled processing power to meet the needs of network, telecommunications, DSP applications, mass storage, and other high-bandwidth systems.

For answers to your technical questions, please visit the Knowledge Center.

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