Documentation

Document PDF Published Date
Embedded Peripherals IP User Guide 2021-06-28
Intel FPGA Software Installation and Licensing 2021-06-21
Intel MAX 10 FPGA Configuration User Guide 2021-07-02
Intel Quartus Prime Pro Edition User Guide: Programmer 2021-07-21
Triple-Speed Ethernet Intel FPGA IP Release Notes 2021-06-23
Triple-Speed Ethernet Intel FPGA IP User Guide 2021-06-29
ALTERA_CORDIC IP Core User Guide 2017-05-08
AN 265: Using Altera MAX Series as Microcontroller I/O Expanders 2014-09-22
AN 294: Crosspoint Switch Matrices in Altera MAX Series 2014-09-22
AN 447: Interfacing Intel FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems 2017-11-06
AN 485: Serial Peripheral Interface Master in Altera MAX Series 2014-09-22
AN 486: SPI to I2C Using Altera MAX Series 2014-09-22
AN 488: Stepper Motor Controller Using Altera MAX Series 2014-09-22
AN 490: Altera MAX Series as Voltage Level Shifters 2014-09-22
AN 491: Power Sequence Auto Start Using Altera MAX Series 2014-09-22
AN 492: CF+ Interface Using Altera MAX Series 2014-09-22
AN 493: I2C Battery Gauge Interface Using Altera MAX Series 2014-09-22
AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX Series 2014-09-22
AN 495: IDE/ATA Controller Using Altera MAX Series 2014-09-22
AN 496: Using the Internal Oscillator IP Core 2017-11-06
AN 498: LED Blink Using Power Sequencing in Altera MAX Series 2014-09-22
AN 500: NAND Flash Memory Interface with Altera MAX Series 2014-09-22
AN 501: Pulse Width Modulation Using Altera MAX Series 2014-09-22
AN 502: Implementing SMBus Controller in Altera MAX Series
AN 509: Multiplexing SDIO Devices Using Altera MAX Series 2014-09-22
AN 730: Nios II Processor Booting Methods in MAX 10 FPGA Devices 2017-02-21
AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor 2017-02-21
AN 831: Intel FPGA SDK for OpenCL Host Pipelined Multithread 2017-11-20
AN752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP) 2015-11-02
Configuring Altera FPGAs 2014-12-15
Errata Sheet and Guidelines for MAX 10 ES Devices 2015-06-12
High-speed Reed-Solomon IP Core Release Notes 2017-11-06
Intel MAX 10 FPGA Device Overview 2017-12-15
Intel MAX 10 High-Speed LVDS I/O User Guide 2017-12-15
Intel Quartus Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization 2017-11-06
LDPC IP Core User Guide 2017-11-06
MAX 10 Embedded Multipliers User Guide 2017-02-21
MAX 10 FPGA Development Kit User Guide 2017-09-07
MAX 10 FPGA Device Architecture 2017-02-21
Nios II Embedded Design Suite Release Notes 2015-06-17
Nios II Flash Accelerator Using Max10 2015-06-30
Nios II Floating Point Hardware 2 Component User Guide
Nios II Gen2 Migration Guide 2015-06-12
PCB Stackup Design Considerations for Intel FPGAs 2017-06-28
Putting Altera MAX Series in Hibernation Mode Using User Flash Memory 2016-01-14
Timing Analyzer Quick-Start Tutorial Intel Quartus Prime Pro Edition 2017-12-01
Using the Altera PDN Tool to Optimize Your Power Delivery Network Design 2015-07-08
Viterbi IP Core User Guide 2017-11-06
AN 522: Implementing Bus LVDS Interface in Supported Intel FPGA Device Families 2018-07-31
AN 630: Real-Time ISP and ISP Clamp for Intel MAX Series Devices 2020-04-13
AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification 2018-09-01
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel Low-Cost FPGAs 2019-04-03
AN 761: Board Management Controller 2018-06-27
AN 773: Drive-On-Chip Design Example for Intel MAX 10 Devices 2021-04-22
AN 812: Platform Designer System Design Tutorial 2018-04-02
AN 834: Using the Intel HLS Compiler Pro Edition with an IDE 2020-05-29
AN 896: Multi-Rail Power Sequencer and Monitor Reference Design 2019-09-30
AN 904: Intel MAX 10 Hitless Update Implementation Guidelines 2020-02-24
AN 918: Using the Intel HLS Compiler Standard Edition with an IDE 2020-05-29
ASMI Parallel II Intel FPGA IP User Guide 2020-07-29
BCH Intel FPGA IP: User Guide 2018-11-30
Battery Management System Reference Design 2016-04-02
Chip ID Intel FPGA IP Cores User Guide 2020-10-05
Creating Heterogeneous Memory Systems in Intel FPGA SDK for OpenCL Custom Platforms 2016-12-13
DDR2 and DDR3 SDRAM Controller with UniPHY IP Core Release Notes 2019-07-01
Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide 2020-10-06
Embedded Design Handbook 2020-07-22
Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide 2020-03-11
Ethernet Design Example Components User Guide 2021-03-29
External Memory Interface Handbook Volume 1: Intel FPGA Memory Solution Overview, Design Flow, and General Information 2017-05-08
External Memory Interface Handbook Volume 2: Design Guidelines 2017-05-08
External Memory Interface Handbook Volume 3: Reference Material 2019-07-24
FFT IP Core: User Guide 2017-11-06
FIFO Intel FPGA IP User Guide 2020-12-14
Floating-Point IP Cores User Guide 2021-03-12
Guidelines for Developing a Nios II HAL Device Driver 2015-06-12
High-speed Reed-Solomon IP Core User Guide 2017-11-06
Intel FPGA Download Cable User Guide 2020-03-11
Intel FPGA Integer Arithmetic IP Cores User Guide 2020-10-05
Intel FPGA SDK for OpenCL Pro Edition: Custom Platform Toolkit User Guide 2020-09-28
Intel FPGA SDK for OpenCL Standard Edition: Custom Platform Toolkit User Guide 2018-09-24
Intel FPGA Software Installation and Licensing Quick Start 2018-11-26
Intel High Level Synthesis Compiler Standard Edition: Best Practices Guide 2019-12-18
Intel High Level Synthesis Compiler Standard Edition: Getting Started Guide 2020-03-26
Intel High Level Synthesis Compiler Standard Edition: Reference Manual 2019-12-18
Intel High Level Synthesis Compiler Standard Edition: User Guide 2019-12-18
Intel High Level Synthesis Compiler Standard Edition: Version 19.1 Release Notes 2019-03-26
Intel MAX 10 Analog to Digital Converter User Guide 2021-05-04
Intel MAX 10 Clocking and PLL User Guide 2021-02-09
Intel MAX 10 Embedded Memory User Guide 2018-06-12
Intel MAX 10 External Memory Interface User Guide 2021-04-01
Intel MAX 10 FPGA Design Guidelines 2020-10-19
Intel MAX 10 FPGA Device Datasheet 2020-06-30
Intel MAX 10 FPGA Device Family Pin Connection Guidelines 2020-06-30
Intel MAX 10 FPGA Signal Integrity Design Guidelines 2021-04-27
Intel MAX 10 General Purpose I/O User Guide 2021-04-27
Intel MAX 10 JTAG Boundary-Scan Testing User Guide 2020-08-11
Intel MAX 10 Power Management User Guide 2018-07-04
Intel MAX 10 User Flash Memory User Guide 2020-06-30
Intel Quartus Prime Design Suite Version 18.1 Update Release Notes 2019-04-17
Intel Quartus Prime Standard Edition Handbook Volume 1 Design and Synthesis 2018-05-09
Intel Quartus Prime Standard Edition Handbook Volume 3 Verification 2018-05-09
Intel Quartus Prime Standard Edition: Version 20.1 Software and Device Support Release Notes 2020-11-23
Intel Quartus Prime Timing Analyzer Cookbook 2018-11-12
Introduction to Intel FPGA IP Cores 2020-11-09
MAX 10 Device Errata 2016-05-16
MAX 10 FPGA 10M50 Evaluation Kit User Guide 2020-04-02
ModelSim - Intel FPGA Edition Simulation Quick-Start: Intel Quartus Prime Standard Edition 2019-12-30
NCO IP Core: User Guide 2017-11-06
Nios II Custom Instruction User Guide 2020-04-27
Nios II Performance Benchmarks 2020-05-14
Nios II Processor Reference Guide 2020-10-22
Nios II Software Developer Handbook 2021-04-02
QDR II and QDR II+ SRAM Controller with UniPHY IP Core Release Notes 2019-07-01
RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core Release Notes 2019-07-01
Reed-Solomon II IP Core User Guide 2016-05-02
The Automotive-Grade Device Handbook 2021-03-01
Triple-Speed Ethernet Intel FPGA IP Release Notes 2021-04-01
Video and Image Processing Suite Release Notes 2019-04-15
Video and Image Processing Suite User Guide 2021-02-12
Virtual JTAG Intel FPGA IP Core User Guide 2020-12-01
Power and Thermal Management
Design Guidelines
End Applications

Online Training

Course Title Description

Introduction to Remote System Upgrade in MAX 10 Devices

 

Learn about Remote System Upgrade (RSU) feature, unique to Intel® MAX® 10 devices that gives you the ability to remotely reconfigure a running device in the field to fix design problems or add functionality without a costly service call or downtime. Dual programming images provide a fail-safe update procedure, automatically falling back to a factory image in case of a problem.

 

This part of the training introduces the need and use cases for RSU and discusses the device resources and design elements required to create a design that makes use of the feature.

Remote System Upgrade in MAX 10 Devices : Design Flow & Demonstration

 

 The second part of the training walks through the complete design flow for an RSU-supported design and includes a software and hardware demonstration of the flow.
Introduction to Analog to Digital Conversion in MAX 10 Devices This training introduces the Intel MAX 10 device family, discusses the typical types and uses of analog-to-digital convertors (ADCs), and presents the architecture of the ADC blocks found in Intel MAX 10 devices.
Integrating Analogue to Digital Conversion in MAX 10 Devices This training discusses how to use the  intellectual property (IP) Parameter Editor to parameterize the ADC and how to integrate the generated IP into a design.
Using the ADC Toolkit in MAX 10 Devices This part of the training discusses how to use the System Console-based ADC Toolkit to graphically analyze converted digital values captured by the ADC.
Using the MAX 10 User Flash Memory
 Intel MAX 10 FPGAs feature internal User Flash Memory that can be used for general purpose non-volatile storage. This training discusses the properties of the User Flash memory as well as how to instantiate and perform operations on the User Flash Memory.
Using the MAX 10 User Flash Memory with the Nios II Processor Intel MAX 10 FPGAs feature internal User Flash Memory that can be used for general purpose non-volatile storage including software storage. This training discusses how to effectively use the User Flash Memory with the Nios II processor in various modes.
Using the Nios II Processor: hardware Development Lean about the Nios II embedded soft processor, the basics of the Avalon® Standard and the Platform Designer (formerly Qsys) high performance network -on-a-programmable-chip architecture.
Using the Nios II Processor: Software Development Learn about the Nios II Software Build Tools for Eclipse, develop software for FPGAs, and use Nios II Development kits for prototyping. Utilize the associated Nios II processor and Platform Designer (formerly Qsys) "Hello World" lab on the low-cost MAX 10 Development Kit to exercise the concepts discussed in the slides and associated tool demonstrations included in the class.

Getting Started

Title Description
How to Begin a Simple FPGA Design This training is for engineers who have never designed an FPGA before. You will learn about the basic benefits of designing with FPGAs and how to create a simple FPGA design using the Quartus® II software  v15.0. If you’ve purchased a Intel® MAX® 10 FPGA Development Kit, you can transfer the programming file created during the tutorial to the development board
Become an FPGA Designer in 4 Hours
 This course gives you basic skills to design with Intel FPGAs. The course uses lecture, demonstrations, and labs that is completed in 4 hours. Learn architectural features of Intel FPGA devices and how the Quartus® II software works.
Using the Nios II Processor: Hardware Development Learn the basics of the Avalon Standard Interface and the Platform Designer's (formerly Qsys) high performance network-on-a-programmable-chip architecture. Learn to use the Platform Designer (formerly Qsys) to develop and configure customized Nios II processor-based hardware systems. Utilize the associated Nios II processor and Platform Designer (formerly Qsys) “Hello World” lab on the MAX 10 Development Kit to exercise the concepts discussed in the slides and associated tool demonstrations included in this class.
Using the Nios II Processor: Software Development
 Learn about the Nios II Software Build Tools for Eclipse v14.1. Learn to develop software for FPGAs and use Nios II Development Kits for prototyping. Utilize the associated Nios II processor and Platform Designer (formerly Qsys) “Hello World” lab on the MAX 10 Development Kit to exercise the concepts discussed in the slides and associated tool demonstrations included in this class.

How-to Videos