This unprecedented flexibility puts you in control of the system, allowing you to make design decisions that reduce costs and increase signal integrity.
Support for CDR-Based Serial Standards
Each receiver CDR block has a unique phase-locked loop (PLL) to allow the data to be received correctly and to correct skew between the channels caused by the transmission line where more than one transceiver is required for a particular protocol. The CDR extracts the clock from the incoming serial data stream and provides a recovered clock that samples the serial data stream and clocks the deserializer. Stratix IV GX transceivers use CDR techniques to support serial standards such as PCI Express, Serial RapidIO®, Gigabit Ethernet (GbE), XAUI/HiGig, the Optical Internetworking Forum (OIF) CEI-6G, Interlaken, SFI-5, GPON, SONET, CPRI, OBSAI, Fibre Channel, HyperTransportTM, SDI, and Altera’s SerialLite II.
Flexible Transceiver PLLs and Clocking Modes
Stratix IV GX FPGAs arrange transceivers in blocks that contain either four or six transceivers. The transceiver blocks can be driven by two different clock sources, each with access to a pair of transmit PLLs. This combination of clocks and PLLs supports four different data rates within a single transceiver block, which allows the block to support multiple protocols if required. The dual-PLL architecture dramatically reduces power dissipation compared to the single-PLL implementation found in competing devices.
Differential I/O Buffer With Dynamically Controllable Settings
The device buffer settings for Stratix IV GX devices are dynamically controllable, which allows you to adjust the settings while the transceiver is running. For example, dynamically reconfigurable, programmable pre-emphasis, and equalization capabilities tailor the data signal to compensate for signal degradation across the transmission medium. A variety of dynamically programmable VOD settings ensure that the drive strength aligns with the line impedance and trace length. Additionally, differential on-chip termination provides the appropriate receiver and transmitter buffer termination for moderate-performance signals.
Architected for Low Power
Transceivers are often used in backplane and inter-board connectivity where cooling is difficult to manage. Therefore, it is important for the transceiver to have minimal power consumption. Stratix IV GX transceivers are architected to support a targeted data range, meeting the “sweet spot” of applications and protocol requirements. This targeted approach, combined with an optimized datapath and clocking, means that the transceivers within Stratix IV GX FPGAs use considerably less power than competing solutions. This can be a considerable savings, as many high-performance applications require multiple transceivers to meet bandwidth requirements. Typical PMA power is 100 mW at 3.2 Gbps,135 mW at 6.375 Gbps, and 165 mW at 8.5 Gbps.
Optimized for Minimal SSN
High-speed I/O and wide high-speed bus interfaces require you to minimize simultaneous switching noise (SSN) to achieve high signal integrity.
Stratix IV GX FPGAs are built on a package design that delivers extremely high immunity to SSN. The devices adopt an aggressive signal-power-ground pin ratio to minimize SSN effects and to account for the embedded transceivers. This ensures that Stratix IV GX devices provide an extremely robust SSN solution.