Stratix® IV GX FPGAs include specific digital functionality to deliver physical coding sublayer (PCS) compliance for a number of key protocols used in backplane, line card, and chip-to-chip applications. These digital blocks are optimized for enhanced protocol support, reducing the amount of resources required in the device to implement the physical layer of the protocol while maintaining a low-power solution. The blocks, when combined with specific intellectual property (IP) and reference designs, can provide a complete protocol solution, both simplifying potentially complex designs and reducing project risk. Table 1 shows the key protocols supported by Stratix IV GX FPGAs.
The PCS block simplifies protocol support by including specific hard logic within the transceiver. Figure 1 shows a block diagram of the Stratix IV GX PCS architecture.
Stratix IV GX PCS provides key features to deliver protocol compliance within the transceiver block. In addition, dedicated state machines are included to support the PCI Express, GbE, and XAUI protocols. The state machines both configure and control the various PCS sub-blocks to support the specified protocol, further simplifying implementation. Tables 2 and 3 show PCS support by protocol.
Table 2. PCS Implementation by Protocol (8B/10B Encoding)
Hard IP is not used. When it is used, the PCS to hard IP interface is 8 bits wide for both Gen1 and Gen2.
Each block within the transceiver is highly configurable to support both industry standard and customer proprietary protocols. Transceiver implementation is simplified within the Quartus® Prime development tool. The tool automatically configures the transceiver PCS block to support the selected protocol, speeding up implementation and reducing design risk. The Quartus Prime software also provides basic configuration modes for proprietary and non-standard protocols.
Built-In Self Test (BIST)
The BIST provides a powerful set of diagnostic capabilities to the transceiver. It includes a pattern generator and checker for pseudo-random binary sequence (PRBS) and others. The BIST also features four loopback configurations that can be used for system diagnostics, allowing interrogation of the physical media attachment (PMA), the PCS, or both the PMA and PCS layers of the transceiver into the FPGA.