Stratix IV GX Transceivers: PCS

Stratix® IV GX FPGAs include specific digital functionality to deliver physical coding sublayer (PCS) compliance for a number of key protocols used in backplane, line card, and chip-to-chip applications. These digital blocks are optimized for enhanced protocol support, reducing the amount of resources required in the device to implement the physical layer of the protocol while maintaining a low-power solution. The blocks, when combined with specific intellectual property (IP) and reference designs, can provide a complete protocol solution, both simplifying potentially complex designs and reducing project risk. Table 1 shows the key protocols supported by Stratix IV GX FPGAs.

Table 1. Stratix IV GX Protocol Support

Protocol Data Rate Complete Solution
PCI Express® Gen1 2.5 Gbps IP
PCI Express Gen2 5.0 Gbps IP
Serial RapidIO® 1.25, 2.5, 3.125 Gbps IP
SerialLite II 622 Mbps–6.375 Gbps IP
OIF CEI-6G 4.976 Gbps–6.375 Gbps -
10-Gigabit Ethernet XAUI 3.125 Gbps IP
HiGig 3.75 Gbps IP
GPON 1.244 Gbps upstream, 2.488 Gbps downstream -
SFI-5 2.488 Gbps–3.125 Gbps -
Gigabit Ethernet (GbE) 1.25 Gbps IP
SDH/SONET OC-12 622 Mbps -
SDH/SONET OC-48 2.488 Gbps -
CPRI 0.6144, 1.288, 2.4576, 3.072 Gbps IP
Fibre Channel 1.0625, 2.125, 4.25, 8.5 Gbps -
HyperTransport™ 2.4, 2.8, 3.2 Gbps -
SD-SDI

270 Mbps (1)

IP
HD-SDI 1.485 Gbps IP
3G-SDI 2.97 Gbps IP
  1. Data rate supported using oversampling
Figure 1. Stratix IV GX PCS Architecture

Physical Coding Sublayer Block

The PCS block simplifies protocol support by including specific hard logic within the transceiver. Figure 1 shows a block diagram of the Stratix IV GX PCS architecture.

Stratix IV GX PCS provides key features to deliver protocol compliance within the transceiver block. In addition, dedicated state machines are included to support the PCI Express, GbE, and XAUI protocols. The state machines both configure and control the various PCS sub-blocks to support the specified protocol, further simplifying implementation. Tables 2 and 3 show PCS support by protocol.

Table 2. PCS Implementation by Protocol (8B/10B Encoding)

Required PCS Functions PCI Express
(Gen1)
PCI Express
(Gen2)
GbE XAUI Serial RapidIO® SerialLite II
Data Rates (Gbps)2.55.01.253.1253.1250.622–6.375
Channel Bonding1, 4, 81, 4, 8141, 4Up to x16
Possible Reference Clock Values (MHz)100100125156.25156.2562.2–622.08
FPGA Bus Width (Bits Per Channel)8 or 16 (4)16 (4)816168, 16, 32
Dedicated Sync State MachineCheckCheckCheckCheck--
Word AlignCheckCheckCheckCheckCheckCheck
Rate MatchCheckCheckCheckCheckCheck-
Byte Serialize/DeserializeCheckCheck-CheckCheckCheck
Phase Compensation FIFO BufferCheckCheckCheckCheckCheckCheck
Byte Reordering------
Single Bit Slip-----Check
Special InterfacePIPE-1.0PIPE-2.0GMII Like (2)XGMII Like (3)--

Table 3. PCS Implementation by Protocol (Scrambled Encoding)

Required PCS Functions CEI-6G SDH/SONET Scrambled Backplane SD-SDI HD-SDI 3G-SDI
Data Rates (Gbps)6.3750.6222.488

0.270 (1)

1.4852.97
Channel Bonding111111
Possible Reference Clock Values (MHz)

155.52– 622.08

62.2, 311.04

77.76, 155.52, 311.04, 622.08

67.5

74.25

74.25

FPGA Bus Width (Bits Per Channel)32816101010
Word Align-CheckCheck---
Rate Match------
Byte Serialize/DeserializeCheck-Check---
Phase Compensation FIFO BufferCheckCheckCheckCheckCheckCheck
Byte Reordering--Check---
Single Bit SlipCheck--Check CheckCheck

Notes to Tables 2 and 3:

  1. Data rate achieved by oversampling.
  2. GMII support for Gigabit Ethernet only.
  3. XGMII has SDR instead of DDR interface.
  4. Hard IP is not used. When it is used, the PCS to hard IP interface is 8 bits wide for both Gen1 and Gen2.

Each block within the transceiver is highly configurable to support both industry standard and customer proprietary protocols. Transceiver implementation is simplified within the Quartus® Prime development tool. The tool automatically configures the transceiver PCS block to support the selected protocol, speeding up implementation and reducing design risk. The Quartus Prime software also provides basic configuration modes for proprietary and non-standard protocols.

Built-In Self Test (BIST)

The BIST provides a powerful set of diagnostic capabilities to the transceiver. It includes a pattern generator and checker for pseudo-random binary sequence (PRBS) and others. The BIST also features four loopback configurations that can be used for system diagnostics, allowing interrogation of the physical media attachment (PMA), the PCS, or both the PMA and PCS layers of the transceiver into the FPGA.