Termination Solutions in Stratix IV FPGAs

As devices switch faster, signal integrity becomes crucial. Stratix® IV FPGAs offer advanced on-chip termination (OCT) technology to further improve signal integrity and simplify PCB design.

  • Altera's proprietary dynamically-controlled, on-chip termination (dynamic OCT)
  • All I/O banks support OCT
  • Supports series, parallel, and differential OCT
  • All new digital automatic calibration circuitry

Table 1 lists key benefits of Dynamic OCT.

Table 1. Benefits of Dynamic OCT

Benefit Description
Reduce Power Consumption Dynamic OCT turns off termination during periods of reads/writes, thereby saving 1.02W on a typical 72-bit interface hence minimizing power.
Improved Signal IntegrityDynamic OCT provides proper line termination and impedance matching on bidirectional buses, which helps prevent reflections on the transmission line.
Simpler Board DesignDynamic OCT removes on-board termination resistor requirements, resulting in a simpler PCB layout.
Lower CostWith dynamic OCT, fewer resistors, fewer traces, and less space are needed on the board. Reducing your layout time and the number of components on the PCB can result in lower overall system costs.
Increased System ReliabilitySystem reliability increases because dynamic OCT reduces the number of components on the PCB.

Dynamic OCT

Stratix IV FPGAs are Altera's second generation of FPGAs with dynamic OCT. Dynamic OCT enables series termination (RS) and parallel termination (RT ) to be dynamically turned on/off during the data transfer. This feature is especially useful when Stratix IV FPGAs are used with external memory interfaces to interface with DDR memories.

The series and parallel terminations are turned on or off depending on the read and write cycle of the interface. During the write cycle, the RS is turned on and the RT is turned off to match the line impedance. During the read cycle, the RS is turned off and the RT is turned on as the Stratix IV FPGA implements the far-end termination of the bus. See Figure 1.

Digital Calibration Circuitry

The new digital calibration circuitry in all Stratix IV FPGA I/O pins allows you to precisely control the impedance value of the OCT resistors.

  • All I/O banks support OCT with automatic calibration
  • Compensates impedance change due to temperature and voltage fluctuation
  • Provides precise impedance control for series and parallel OCT
  • Calibration can be enabled by user-controlled signals during device operation or by default during device configuration
  • Pull-up/pull-down external resistors required on board as reference

Series Termination

Stratix IV FPGAs support on-chip series termination for LVTTL, LVCMOS, and SSTL single-ended I/O standards. OCT is provided at the output signal to match the impedance of the transmission line, typically 25 Ω or 50 Ω. You can use this termination in many general-purpose applications and to interface with external memories such as DDR SDRAM. Stratix IV FPGA on-chip series termination supports dynamic OCT, which is useful for bidirectional interfaces (see Figure 2).

Parallel Termination

Stratix IV FPGAs support on-chip parallel termination. Parallel termination is extremely useful for applications such as interfacing with external memories where I/O standards such as HSTL and SSTL are used. Stratix IV FPGA parallel termination supports dynamic OCT, which is useful for bidirectional interfaces (see Figure 3).

Differential Termination

Stratix IV FPGAs support input on-chip differential termination for high-speed differential signals such as LVDS (see Figure 4).

In addition to OCT, Stratix IV FPGAs also support external termination schemes, as shown in Table 2.

Table 2. Termination Solutions Support

Termination Type On-Chip External
SeriesCheck MarkCheck Mark
ParallelCheck MarkCheck Mark
DifferentialCheck MarkCheck Mark