Single Event Upset

Single event upsets (SEUs) are caused by ionizing radiation strikes that discharge the charge in storage elements such as configuration memory cells, user memory, and registers. In terrestrial applications, the two ionizing radiation sources of concern are alpha particles emitted from package impurities and high-energy neutrons caused by the interaction of cosmic rays with the earth's atmosphere.

Soft errors are random and happen according to a probability related to energy levels, flux, and cell susceptibility. An important consideration of soft errors is that they can always be recovered simply by rewriting a cell with the correct value. No power cycle is needed since there is no silicon latch-up.

Through process and design techniques, Altera has improved the soft error rate with every technology generation. We measure the soft error rate using standard test procedures defined by JEDEC's JESD-89 spec. We introduced the industry's first automatic cyclic redundancy check (CRC) checker and removed the extra logic and complexity requirements common to other CRC solutions.

SEU testing of Altera® FPGAs at Los Alamos Neutron Science Center (LANSCE) has revealed the following results:

  • SEUs do not induce latch-up in Altera FPGAs
  • No SEU errors have been observed in hard CRC circuit and I/O registers
  • The CRC circuit can detect all single-bit and multi-bit errors within the configuration memory
  • There's a Mean Time Between Functional Interrupt (MTBFI) of hundreds of years,
    even for very large, high-density FPGAs (the EP2S180 device was tested at sea level)

Altera's Stratix® series, Arria® GX series, and Cyclone® series of FPGA families feature built-in dedicated hard circuitry to continually and automatically check CRC at no extra cost. You can easily set up the CRC checker through Quartus® II software.