During the write cycle, RS is turned on and RT is turned off to match the line impedance
During the read cycle, RS is turned off and RT is turned on as the Stratix series FPGA implements the far-end termination of the bus
For additional information on DDR3 and dynamic OCT, refer to the 40-nm Power Management and Advantages white paper (PDF).
Process and Circuit Technologies
Stratix III and later Stratix series FPGAs utilize the latest process and circuit techniques along with major circuit and architecture innovations to minimize power and still deliver the highest performance of any FPGA. Some of the technologies employed include multi-threshold transistors, variable gate-length transistors, low-k dielectric, triple-gate oxide (TGO), super-thin gate oxide, and strained silicon. For additional information on these process and circuit technologies, refer to the 40-nm Power Management and Advantages white paper (PDF).
PowerPlay Power Analysis and Optimization Tool
The Quartus II software PowerPlay power analysis and optimization tool helps keep the total power consumption of your designs to a minimum. Altera began offering advanced power optimization capabilities in Quartus II software in 2005, and it immediately provided an average 25 percent reduction in dynamic power in our customers’ designs.
Since then, the PowerPlay power analysis and optimization tool has been improved with the addition of intelligent decision making in synthesis, placement, and routing. Today, by working in conjunction with Programmable Power Technology in the Stratix series silicon, the power consumption minimizing capability of PowerPlay power optimization is the best it has ever been. To learn more, visit the Power Optimization for Stratix III FPGAs web page.