Designers needing lower costs, more density, and functionality for high-volume applications can take advantage of more advanced device families in this series. These newer Cyclone families strengthen our leadership position in solutions for high-volume, low-cost applications.

Section I. Cyclone FPGA Family Data Sheet

Section II. Clock Management

Section III. Memory

Section IV. I/O Standards

Section V. Design Considerations

Section VI. Configuration

Section VII. PCB Layout Guidelines

Cyclone FAQ

Following are the most frequently asked questions about the Cyclone® FPGA family.



System Clock Management

I/O Standards and Memory Interfaces

Software and Intellectual Property

Device Configuration

Nios Soft-Core Embedded Processors



What is the Cyclone series?

Cyclone series FPGAs provide the benefits of programmable logic at price points competitive with ASICs and ASSPs. Built from the ground up based on extensive input from hundreds of customers, these low-cost devices provide high-volume, application-focused features such as embedded memory, external memory interfaces, and clock management circuitry.

What is the Cyclone family of FPGAs?

The Cyclone FPGA family is the first generation of the low-cost Cyclone FPGA series. Designed to make the benefits of programmable logic more accessible to a broader market, we developed Cyclone FPGAs specifically for high-volume applications that previously were driven by cost pressures to standard products or ASICs. The Cyclone FPGA family has the perfect mix of features, density, and performance at less than $0.99 per 1,000 logic elements (LEs). Finally, system designers building high-volume applications in the consumer, communications, computer peripheral, industrial, and automotive markets now have access to the flexibility, economic efficiencies, and time-to-market advantages of programmable logic.

With densities ranging from 2,910 to 20,060 logic elements (LEs), Cyclone devices are optimized for maximum logic capacity for the lowest cost. Cyclone devices feature up to 288-Kbits of embedded memory, PLLs, and support for external memory interfaces and differential and single-ended I/O standards.

What were the criteria used to design the Cyclone FPGA family?

We included hundreds of customers from different market segments in the product definition process to identify the price threshold, features, and performance required to address high-volume applications. In addition, we used a ground-up approach to design the Cyclone device family, using the same methodology used to define the Stratix device family. The result is the Cyclone family: the lowest-cost FPGAs ever with the right mix of device capabilities.

Which markets does the Cyclone FPGA family address?

The Cyclone device family is the optimum low-cost solution for high-volume applications in a wide variety of markets including high-end consumer electronics, leading-edge communications, computer peripherals, industrial, and automotive. Cyclone devices provide a number of features optimized for volume applications such as plasma display panel modules, mid-range and low-end routers, and automotive electronics systems. Learn more about automotive-grade versions of Cyclone FPGAs.

Why are Cyclone FPGAs an ideal alternative to ASICs?

Cyclone devices enable the development of new, programmable solutions in volume-driven applications where FPGAs were once considered too expensive. ASICs have high non-recurring engineering (NRE) costs, expensive design tools, and significant overall risk in bringing products to market in a timely manner. The historical price gap between an FPGA and an ASIC meant that a customer could recover the ASIC NRE charges at volumes near 10,000 units. The crossover point is anywhere from 100,000 units to 5 million units. Now you have access to the benefits of programmable logic at ASIC prices.

What are the members of the Cyclone FPGA family, and what packages are offered?

The Cyclone FPGA family includes five members ranging in density from 2,910 to 20,060 LEs (see Table 1). Low-cost packages with vertical migration support are available for Cyclone devices, including thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine BGA (FBGA) packages (see Table 2).

Table 1. Cyclone Family Device Overview
Device Logic Elements Maximum PLLs M4K RAM Blocks Total RAM Bits Maximum User I/O Pins
EP1C3 2,910 1 13 59,904 104
EP1C4 4,000 2 17 78,336 301
EP1C6 5,980 2 20 92,160 185
EP1C12 12,060 2 52 239,616 249
EP1C20 20,060 2 64 294,912 301
Table 2. Cyclone Device Package Options and User I/O Pin Counts
Device 100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin
FineLine BGA
FineLine BGA
FineLine BGA
EP1C3 65 104 - - - -
EP1C4 - - - - 249 301
EP1C6 - 98 185 185 - -
EP1C12 - - 173 185 249 -
EP1C20 - - - - 233 301

What is the process technology for the Cyclone FPGA family?

The Cyclone FPGA family is based on a cost-optimized 1.5-V, 0.13µm, all-layer-copper process from TSMC.

Why is there a density overlap between Cyclone and Stratix devices?

There is a density overlap between Cyclone and Stratix devices to address different market requirements. Stratix devices are the industry's highest-performance and highest-density FPGAs with robust features for high-end applications. Cyclone devices are the industry's lowest-cost FPGA. The features and capabilities of Cyclone devices have been targeted for high-volume applications where the most critical factor is price.

How do Cyclone FPGAs compare to Stratix FPGAs?

The Cyclone and Stratix FPGA families were built to address different market needs. However, Cyclone devices share some similarities with Stratix devices, such as:

  • Core Voltage: 1.5 V
  • Process: all-layer-copper process
  • LEs: units of logic containing a 4-input look-up-table (LUT) and a programmable register
  • Memory Blocks: 4-Kbit memory blocks (M4K RAM blocks)

Are Cyclone devices pin-compatible with Cyclone II, ACEX, and Stratix devices?

No, Cyclone devices are based on a completely new architecture and are not pin-compatible with the Cyclone II, ACEX, or Stratix devices.

How do Cyclone device ordering codes relate to their respective densities?

Cyclone device ordering codes are based on the number of available LEs in the device. All Cyclone device ordering codes begin with EP1C. The digits that follow indicate the number of LEs divided by a factor of 1,000. For example, the largest Cyclone device is the EP1C20 device which has 20,060 LEs.

Why are fewer user I/O pins available when you migrate to a higher-density device in the same package?

Each device in the Cyclone FPGA family is optimized for the highest possible number of I/O pins in the smallest density. Larger-density members require a larger number of power and ground pins to operate correctly due to higher LE counts; therefore, when placed in the same package, the number of available user I/O pins must be reduced.



What type of embedded memory and memory features do Cyclone FPGAs have?

The Cyclone embedded memory consists of columns of 4-Kbit RAM blocks, each capable of data transfer rates of over 200 MHz. Each RAM block can implement various types of memory, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers, and include extra parity bits for error control, mixed-width mode, and mixed-clock mode support.


System Clock Management

What type of system clock management solution is offered in Cyclone FPGAs?

Cyclone FPGAs provide a global clock network and PLLs with on-and-off-chip capabilities for a complete system clock management solution.

What does the global clock network consist of, and what can it be used for in Cyclone FPGAs?

Each Cyclone device has eight global clock lines that are combined into a single global clock network that is accessible throughout the entire device. The clock network is optimized to minimize skew, providing clock, clear, and reset signals to all resources within the device.

How many dedicated global clock inputs are available per device?

Cyclone devices have four dedicated clock input pins that feed the global clock network lines directly, except for the EP1C3 device in the 100-pin TQFP package, which has two dedicated clock input pins.

How many PLLs are available in Cyclone FPGAs? What PLL features are available?

Cyclone devices contain two PLLs, except for the EP1C3 device, which contains one. These PLLs provide general-purpose clocking management capabilities, such as multiplication and phase shifting, a programmable duty cycle, as well as outputs for differential I/O support. The external clock outputs, one per PLL, can be used to provide clocks to other devices in the system, eliminating the need for other clock-management devices on the board.

I/O Standards and Memory Interfaces

Designers needing lower costs, more density, and functionality for high-volume applications can take advantage of Cyclone II FPGAs, the second-generation in the Cyclone series.

Which external memory interfaces do Cyclone FPGAs support?

The Cyclone FPGA family external memory interface solution includes dedicated, speed-optimized circuitry to interface with SDR SDRAM, DDR SDRAM, and fast cycle memory (FCRAM) devices at data rates up to 266 Mbps using a 133-MHz clock. Table 3 shows the clock speed and maximum data transfer rate for each memory interface.

Table 3. Cyclone Devices External Memory Interface Support

Memory Device Type Supported Clock Speed Maximum Data Transfer Rate
SDR SDRAM133 MHz133 Mbps
DDR SDRAM133 MHz266 Mbps
FCRAM133 MHz266 Mbps

What single-ended I/O electrical standards are supported in Cyclone FPGAs?

Cyclone FPGAs support a variety of single-ended I/O standards, including LVTTL, LVCMOS, SSTL, and PCI. Single-ended I/O standards provide more current drive capacity than differential I/O standards, and they are critical when working with advanced memory devices such as DDR SDRAM devices. Cyclone FPGAs support a programmable drive strength control for certain I/O standards with settings ranging from 2 mA up to 24 mA. Table 4 lists the single-ended I/O standards supported in Cyclone FPGAs and their respective performance.

Table 4. Cyclone FPGAs Single-Ended I/O Standards Support

I/O Standard Performance Typical Application
3.3-V/2.5-V/1.8-V LVTTL250 MHzGeneral purpose
3.3-V/2.5-V/1.8-V/1.5-V LVCMOS250 MHzGeneral purpose
SSTL-3 Class I and II166 MHzSDRAM
SSTL-2 Class I and II200 MHzDDR SDRAM
3.3-V PCI66 MHzPC and embedded

What differential I/O electrical standards are supported in Cyclone FPGAs?

Cyclone FPGAs support LVDS on up to 129 channels. Cyclone devices are equipped with LVDS input buffers for receiving high-speed data at up to 640 Mbps. On the transmission side, Cyclone devices require an external resistor network to convert the output to the appropriate LVDS swing levels.


Software and Intellectual Property

What versions of the Quartus II design software support Cyclone FPGAs?

The Quartus II design software, available through the Software Subscription Program, supports all Cyclone devices.

With new features and enhancements such as integrated Verilog and VHDL synthesis, the timing closure methodology, the SignalProbe incremental verification feature, Linux support, and the fast fit compiler option (allowing compile time and performance tradeoffs), the Quartus II software offers a truly integrated, single-platform development tool that minimizes overall development time. The advanced PowerFit technology optimally places-and-routes designs, resulting in efficient resource usage and maximized performance.

Which third-party tools support Cyclone FPGAs?

Synthesis and simulation tools from leading EDA vendors such as Mentor Graphics®, Synplicity, and Synopsys support the Cyclone FPGA family, ensuring the highest quality of results in our devices.

  • Mentor Graphics LeonardoSpectrumTM version 2002d and ModelSim® version 5.6a software and later
  • Synplicity Synplify 7.2 software and later
  • Synopsys FPGA Compiler II version 3.8 software and later

What intellectual property (IP) cores are available for Cyclone FPGAs?

Over 30 IP cores are available for Cyclone FPGAs. Various IP cores from us and our partners are specifically optimized for the Cyclone architecture, including the following:

  • 10/100 Ethernet MAC
  • SDR SDRAM Controller
  • DDR SDRAM Controller
  • FCRAM Controller
  • PCI32 Nios Target
  • SPI Programming Reference Design
  • Finite impulse response (FIR) Filter
  • Nios II Embedded Processor
  • SOPC Builder & Peripherals


Device Configuration

What configuration devices are available to support Cyclone FPGAs?

A series of low-cost serial configuration devices are available that support the Cyclone FPGA family. Each configuration device costs on average 10 percent of its corresponding Cyclone device. Like Cyclone devices, these serial configuration devices provide the lowest cost in programmable logic industry. This combination of Cyclone and serial configuration devices provides the industry's lowest-cost system-on-a-programmable-chip (SOPC) solution.

Why is there a separate serial configuration device family for Cyclone FPGAs instead of combining all the functionality into one device?

The use of configuration devices to configure FPGAs has been decreasing over time. System designers are moving away from using configuration devices, preferring other types of configuration methods, such as flash or microprocessors. To offer the lowest-cost solution for designers who prefer configuration devices as the configuration method of choice, we offer a separate low-cost serial configuration device family to support Cyclone FPGAs. Integrating configuration capabilities inside the Cyclone devices increases the die size, resulting in a higher development cost.


Nios II and Nios Soft Embedded Processors

Are the Nios II and Nios embedded processors supported in Cyclone FPGAs?

Yes, the Nios II and Nios embedded processors contain full support for the Cyclone FPGA family. Cyclone devices with integrated Nios processors can address your needs for low-cost, configurable, embedded processors for a wide range of price-sensitive applications. Additionally, the SOPC Builder development tool shipped with the Nios Development Kit and Quartus II design software introduces a new memory interface that gives you access to our serial configuration devices as system memory.


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