What is the process technology for the Cyclone FPGA family?
The Cyclone FPGA family is based on a cost-optimized 1.5-V, 0.13µm, all-layer-copper process from TSMC.
Why is there a density overlap between Cyclone and Stratix devices?
There is a density overlap between Cyclone and Stratix devices to address different market requirements. Stratix devices are the industry's highest-performance and highest-density FPGAs with robust features for high-end applications. Cyclone devices are the industry's lowest-cost FPGA. The features and capabilities of Cyclone devices have been targeted for high-volume applications where the most critical factor is price.
How do Cyclone FPGAs compare to Stratix FPGAs?
The Cyclone and Stratix FPGA families were built to address different market needs. However, Cyclone devices share some similarities with Stratix devices, such as:
- Core Voltage: 1.5 V
- Process: all-layer-copper process
- LEs: units of logic containing a 4-input look-up-table (LUT) and a programmable register
- Memory Blocks: 4-Kbit memory blocks (M4K RAM blocks)
Are Cyclone devices pin-compatible with Cyclone II, ACEX, and Stratix devices?
No, Cyclone devices are based on a completely new architecture and are not pin-compatible with the Cyclone II, ACEX, or Stratix devices.
How do Cyclone device ordering codes relate to their respective densities?
Cyclone device ordering codes are based on the number of available LEs in the device. All Cyclone device ordering codes begin with EP1C. The digits that follow indicate the number of LEs divided by a factor of 1,000. For example, the largest Cyclone device is the EP1C20 device which has 20,060 LEs.
Why are fewer user I/O pins available when you migrate to a higher-density device in the same package?
Each device in the Cyclone FPGA family is optimized for the highest possible number of I/O pins in the smallest density. Larger-density members require a larger number of power and ground pins to operate correctly due to higher LE counts; therefore, when placed in the same package, the number of available user I/O pins must be reduced.
What type of embedded memory and memory features do Cyclone FPGAs have?
The Cyclone embedded memory consists of columns of 4-Kbit RAM blocks, each capable of data transfer rates of over 200 MHz. Each RAM block can implement various types of memory, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers, and include extra parity bits for error control, mixed-width mode, and mixed-clock mode support.
System Clock Management
What type of system clock management solution is offered in Cyclone FPGAs?
Cyclone FPGAs provide a global clock network and PLLs with on-and-off-chip capabilities for a complete system clock management solution.
What does the global clock network consist of, and what can it be used for in Cyclone FPGAs?
Each Cyclone device has eight global clock lines that are combined into a single global clock network that is accessible throughout the entire device. The clock network is optimized to minimize skew, providing clock, clear, and reset signals to all resources within the device.
How many dedicated global clock inputs are available per device?
Cyclone devices have four dedicated clock input pins that feed the global clock network lines directly, except for the EP1C3 device in the 100-pin TQFP package, which has two dedicated clock input pins.
How many PLLs are available in Cyclone FPGAs? What PLL features are available?
Cyclone devices contain two PLLs, except for the EP1C3 device, which contains one. These PLLs provide general-purpose clocking management capabilities, such as multiplication and phase shifting, a programmable duty cycle, as well as outputs for differential I/O support. The external clock outputs, one per PLL, can be used to provide clocks to other devices in the system, eliminating the need for other clock-management devices on the board.
I/O Standards and Memory Interfaces
Designers needing lower costs, more density, and functionality for high-volume applications can take advantage of Cyclone II FPGAs, the second-generation in the Cyclone series.
Which external memory interfaces do Cyclone FPGAs support?
The Cyclone FPGA family external memory interface solution includes dedicated, speed-optimized circuitry to interface with SDR SDRAM, DDR SDRAM, and fast cycle memory (FCRAM) devices at data rates up to 266 Mbps using a 133-MHz clock. Table 3 shows the clock speed and maximum data transfer rate for each memory interface.