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Section I. Device Core

Section II. I/O Interfaces

Section III. System Integration

Section I. Cyclone III Device Data Sheet

Cyclone III FAQ

Following are answers to the most frequently asked questions about Altera® Cyclone® III FPGAs.


Embedded Multipliers

Embedded Memory

System Clock Management

I/O Standards and Memory Interfaces

Software and Intellectual Property

Nios II Embedded Processors

Device Configuration


What is the Cyclone III device family?

The Cyclone III device family is a low power, high functionality, low cost family of FPGAs designed to support a wide range of cost-sensitive high-volume applications. With this third generation in the Cyclone series, Altera continues to deliver the lowest development and system costs. The low-cost Cyclone III device family contains eight family members ranging from 5K to 120K logic elements (LEs) available in a wide range of low-cost packages.

What process technology does Altera use to build Cyclone III FPGAs?

Cyclone III FPGAs are manufactured on 300-mm wafers using Taiwan Semiconductor Manufacturing Company's (TSMC’s) 65-nm (nine metal layers, all copper) low-power (LP) process technology, designed for low dynamic power and low leakage power.

What is unique about Cyclone III FPGAs?

Cyclone III FPGAs offer an unprecedented combination of low power, high functionality, and low cost. All FPGAs in Altera's Cyclone series are built from the ground up for low-cost, high-volume applications, and Cyclone III FPGAs offer lower power and better performance at a lower cost than competing low-cost FPGAs. Altera also offers you the most complete and most productive development tools with Quartus® II design and development software, low-cost development kits, proven IP cores, and application-specific reference designs.

What markets does the Cyclone III device family target?

Dataquest projects 14 percent CAGR for the overall PLD market between 2004 and 2010, with the fastest growing markets in the automotive and consumer industries. Given the cost-sensitive nature of these applications, they will be serviced primarily by low-cost FPGAs such as the Cyclone III device family. The wireless communication market will also be important for the Cyclone III device family with its low power, higher densities, and higher levels of functionality compared to the previous Cyclone generation. Specific applications include wireless basestations, software defined radio, displays, as well as video and image processing.

What new applications do Cyclone III FPGAs enable and how?

Please refer to the Cyclone III FPGA end-market applications overview page for details about new applications enabled by Cyclone III FPGAs.

How have Cyclone III FPGAs been optimized for power?

The Cyclone III family takes advantage of several techniques such as the use of TSMC's 65-nm low-power process technology and the unique power management features in the Quartus II development software to deliver up to a 50 percent power reduction from the 90-nm Cyclone II device family and up to a 75 percent power advantage over competing FPGAs. TSMC's 65-nm LP process has been fine tuned to provide the lowest static and dynamic power consumption for applications in the portable and consumer markets such as DVRs, handsets, and portable media players. The PowerPlay power analysis and optimization technology in Quartus II development software automatically analyzes and optimizes designs for power consumption while still achieving timing and performance requirements. Low-power benefits include: operations in thermally challenging environments, elimination or reduction in cooling system costs, and extended battery life for portable applications.

How have Cyclone III FPGAs been optimized for low cost?

Cyclone III FPGAs take advantage of the benefits of 65-nm technology (small die size, high density, and low cost) with up to three speed grades higher performance than competing low-cost FPGAs. Cyclone III devices also use staggered I/O rings to reduce die size and board space. A wide selection of low-cost packaging options and support for low-cost configuration devices also enable Altera to offer the lowest cost FPGA solution.

Altera's ability to quickly move Cyclone III devices into high volume also contributes to the device family’s low cost. Altera’s strategy is to be first to volume on new product announcements, giving you the highest quality products when you want them, and in the quantity you need. Altera works in close collaboration with foundry partner TSMC to solve all critical issues, including design for manufacturability (DFM) and performance optimization, early in the life of each new process. Together, the design and process teams work to overcome the technological challenges of each process node and ensure that Altera continues to successfully lead the industry in volume production.

What performance improvements have been made to the Cyclone III device family?

Because the 90-nm Cyclone II device family already offers three speed grades higher performance versus competing FPGA families, Altera chose to improve power, functionality, and cost for the Cyclone III device family and kept the core logic performance on par with the Cyclone II device family. Performance improvements have been made to the embedded multipliers, onboard memory, external memory interface, and I/O.

How do Cyclone III FPGAs compare to Cyclone II FPGAs?

Compared to the previous generation built on the 90-nm process, the 65-nm Cyclone III device family delivers 1.7x higher density, more than 3.5x the embedded memory, and 2x more multipliers, while lowering the cost per LE by 20 percent. Cyclone III FPGAs consume 50 percent less (core) power than Cyclone II FPGAs. Cyclone III FPGAs also offer low-cost configuration options with support for industry-standard commodity parallel flash devices. Cyclone III FPGAs also support higher speed memory interfaces and offer higher I/O and PLL flexibility than Cyclone II FPGAs.

Please refer to the differences between Cyclone III and Cyclone II FPGAs feature comparison page for more details.

How do Cyclone III FPGAs compare to Stratix III FPGAs?

As the high-performance device family, Stratix® III FPGAs offer significantly higher densities, between 47,500 and 338,000 equivalent LEs, more memory, and dedicated digital signal processing (DSP) blocks. For more details on Stratix III FPGAs, please visit the Stratix III device family home page.

What are the members of the Cyclone III device family, and what packages are offered?

The Cyclone III device family contains eight members, ranging from 5K logic elements (LE) to 120K LEs. Low-cost packages with vertical migration support are available for Cyclone III devices, including the thin quad flat pack (TQFP), plastic quad flat pack (PQFP), FineLine BGA packages, and Ultra FineLine BGA packages.

Please refer to the Cyclone III family overview page for more details.

When will all of the Cyclone III devices be available?

All Cyclone III devices are shipping in production now.

When can I start designing with Cyclone III FPGAs?

You can begin your Cyclone III designs today by downloading and installing the free Quartus II Web Edition software with support for density levels exceeding 100K LEs. With the easy-to-use Quartus II software, Altera delivers the lowest development cost and fastest time to design completion to ensure a smooth and successful design flow.

Can I migrate my Cyclone FPGA or Cyclone II FPGA designs to a Cyclone III FPGA?

No, Cyclone III FPGAs are not pin-compatible with Cyclone II or Cyclone FPGAs. The primary design goal for the Cyclone III device family was to provide an unprecedented combination of low power, high functionality, and low cost. Pin compatibility within the Cyclone series would not allow the architecture to be optimized for the Cyclone III device family.

How can I transfer my existing Altera FPGA design to target a Cyclone III FPGA?

Existing Altera FPGA designs can be retargeted to a Cyclone III FPGA in the Quartus II software starting in version 7.0. This will require a recompile of the design.

How many power supplies do you need on board for Cyclone III FPGAs?

Cyclone III FPGAs require a minimum of two power supplies on board: one for VCCINT (1.2 V), one for VCCA_PLL (2.5 V) and one for VCCIO (3.3 V, 3.0V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V) that is user-controllable.

Embedded Multipliers

What type of embedded multipliers do Cyclone III FPGAs have?

Cyclone III FPGAs offer up to 288 embedded 18 x 18 multipliers capable of running at 260 MHz. The embedded multipliers can also be configured as two 9 x 9 multipliers, offering up to 566 9 x 9 multipliers. These multipliers are capable of efficiently implementing multiplication operations commonly found in DSP applications. Embedded multipliers in Cyclone III FPGAs can boost overall system performance and decrease system costs for cost-sensitive DSP applications.

Please refer to the Cyclone III embedded multipliers page for more details.

Embedded Memory

What type of embedded memory and memory features do Cyclone III FPGAs have?

Cyclone III FPGAs offer up to 4 Mbit of embedded memory. The embedded memory consists of columns of 9-Kbit (M9K) RAM blocks, each capable of data transfer rates up to 260 MHz. Each M9K RAM block can implement various types of memory, including true dual-port, simple dual-port, and single-port RAM, ROM, and first-in first-out (FIFO) buffers. Each block also includes extra parity bits for error control, mixed-width mode, and mixed-clock mode support.

Please refer to the Cyclone III embedded memory page for more details.

System Clock Management

What type of system clock management solution is offered in Cyclone III FPGAs?

Cyclone III FPGAs provide a global clock network and PLLs with on- and off-chip capabilities for a complete system clock management solution. Cyclone III FPGAs have up to sixteen dedicated clock input pins that feed the global clock network lines directly.

What does the global clock network consist of and what can it be used for in Cyclone III FPGAs?

The global clock network in Cyclone III FPGAs consists of twenty global clock lines accessible throughout the entire device. It is optimized to minimize skew, providing clock, clear, and reset signals to all resources within the FPGA.

How many PLLs are available in Cyclone III FPGAs? What PLL features are available?

Cyclone III FPGAs offer up to four PLLs. These PLLs provide general-purpose clocking management capabilities such as multiplication and phase shifting, programmable duty cycle, programmable bandwidth, spread spectrum input clocking, lock detection, as well as outputs for differential I/O support. The external clock outputs (one per PLL) can be used to provide clocks to other devices in the system, eliminating the need for other clock-management devices on the board.

Please refer to the Cyclone III system clock management page for more details.

I/O Standards and Memory Interfaces

What single-ended I/O electrical standards are supported in Cyclone III FPGAs?

Cyclone III FPGAs support a variety of single-ended I/O standards, including LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X. Single-ended I/O standards provide more current drive capacity than differential I/O standards, and they are critical when working with advanced memory devices such as DDR, and DDR2 SDRAM, and QDRII SRAM devices. Cyclone III FPGAs also support a programmable drive strength control for certain I/O standards with settings ranging from 2 mA up to 16 mA.

What differential I/O electrical standards are supported in Cyclone III FPGAs?

Cyclone III FPGAs provide support for LVDS, mini-LVDS, RSDS, and LVPECL. LVDS performance is 840 Mbps for transmit data and 875 Mbps for receive data. On the transmission side, Cyclone III FPGAs do not require an external resistor network to convert the output to the appropriate LVDS swing levels.

Which external memory interfaces do Cyclone III FPGAs support?

Cyclone III FPGAs support dedicated, speed-optimized circuitry to interface with SDR, DDR and DDR2 SDRAM devices, and QDRII SRAM devices at up to 400 Mbps with an auto-calibrating PHY for fast timing closure.

Please refer to the Cyclone III interfaces and protocol support page for more details.

Software and Intellectual Property

What versions of the Quartus II development software support Cyclone III FPGAs?

The Quartus II Subscription software and the free Quartus II Web Edition software version 7.0 and later offer design capability for Cyclone III FPGAs. Programming file generation for Cyclone III FPGAs will be supported in a subsequent software release.

The Quartus II development software version 7.0 includes new updates to the SOPC Builder system development tool and the Nios® II embedded processor family to support Cyclone III FPGAs. Updates have also been made to the TimeQuest timing analyzer and SDC timing constraints in support of Cyclone III FPGAs for quick timing closure of high-speed source synchronous interfaces (such as DDR and DDR2) and clock multiplexing design structures. With the PowerPlay power analysis and optimization feature, you can automatically achieve lower power in your design with a push-button compilation.

Which third-party tools support Cyclone III FPGAs?

Synthesis and simulation tools from leading EDA vendors (Cadence, Mentor Graphics®, Synopsys, and Synplicity) support the Cyclone III device family, ensuring the highest quality of results in Altera devices.

What intellectual property (IP) cores are available for Cyclone III FPGAs?

More than 40 proven IP cores are optimized for Cyclone III FPGAs. Various IP cores from Altera and Altera Megafunction Partners Program (AMPPSM) partners are specifically optimized for the Cyclone III FPGA architecture, including:

  • Nios II Embedded Processor
  • Video and Image Processing Suite of nine commonly used IP functions
  • PCI Compiler
  • FIR Compiler
  • NCO Compiler
  • POS-PHY Compiler
  • Reed Solomon Compiler
  • Viterbi Compiler

Nios II Embedded Processors

Is the Nios II family of embedded processors supported in Cyclone III FPGAs?

Yes, Cyclone III FPGAs support the Nios II embedded processor, Altera's obsolescence-free, user-configurable, general-purpose RISC, embedded soft processor family. Second-generation Nios II embedded processors extend Altera's embedded soft processor leadership with better performance, lower cost, and the most complete set of software development tools available anywhere. The Cyclone III device family can incorporate multiple Nios II embedded processors in one FPGA, providing savings in cost, footprint, and power efficiency. Cyclone III FPGAs provide you with maximum flexibility to balance performance needs and device resource usage by supporting three distinct Nios II cores, each optimized for a particular price and performance range. All three cores support a single instruction set architecture, making them 100 percent code-compatible.

Device Configuration

What configuration devices are available to support Cyclone III FPGAs?

To offer the lowest total solution cost, the Cyclone III device family is supported by a low-cost serial configuration device family. On average, these serial configuration devices are priced for volume applications as low as 10 percent of the price of the corresponding Cyclone III FPGA. Four serial configuration devices (1-Mbit, 4-Mbit, 16-Mbit, and 64-Mbit) are offered in space-saving 8-pin and 16-pin small-outline integrated circuit (SOIC) packages.

Cyclone III FPGAs also support configuration using industry standard parallel flash devices from Intel without the need for an external host.