Altera's Cyclone® III LS FPGAs are the first devices to implement a suite of security features at the silicon, software, and intellectual property (IP) level on a low-power, high-functionality FPGA platform. This suite of security features protects your IP from tampering, reverse engineering, and counterfeiting.
The suite of security features in Cyclone III LS FPGAs consists of:
- 256-bit AES bitstream encryption
- JTAG port protection
- Internal oscillator
- Zeroization (active clear)
- Cyclical redundancy check (CRC)
- Design separation
- Supervisor IP
Silicon Security Features
The silicon security features of Cyclone III LS devices protect the FPGA design before, during, and after configuration. All Altera® devices restrict the direct readback of the FPGA configuration via the JTAG port, but the Cyclone III LS FPGA goes beyond this level of protection to give you increased control over access to the full JTAG port. Furthermore, the bitstream is protected during configuration using a 256-bit AES encryption algorithm. Once the design is functional, the Cyclone III LS FPGA ensures the system remains secure using CRC to monitor configuration changes and an internal oscillator as an uninterruptible clock source. In the event a problem is detected, the FPGA can clear itself using the zeroization feature. Figure 1 shows the various Cyclone III LS FPGA security features available on silicon.