Cyclone® III FPGAs support serial, bus, and network interfaces, as well as a wide range of communications protocols. These interfaces and protocols are commonly used in many industrial, communications, and an increasing number of consumer applications.
- Consumer Digital Display Standards
- PCI Express
- SDRAM and SRAM Interfaces
- Ethernet Protocols
- Serial Bus Interfaces
- Communications Protocols
Altera offers a variety of intellectual property (IP) cores for these protocols that are optimized for the Cyclone III FPGA architecture.
FPD–Flat panel display (FPD) link is a National Semiconductor-defined LVDS-based link between a host panel and display panel in an LCD monitor and television platform. Cyclone III FPGAs are predominantly placed at the receive-end of the FPD link to meet the maximum data rate requirement of 805 Mbps. A single FPD link channel consists of four LVDS data pairs and a source-synchronous clock pair, and Cyclone III FPGAs support up to two such channels.
RSDS–Reduced swing differential signaling (RSDS) is a National Semiconductor defined signaling standard primarily used for display applications with resolutions between video graphics arrays (VGAs) and ultra extended graphic arrays (UXGAs). It is a chip-to-chip protocol and links the flat-panel timing controllers to the column drivers. RSDS is a differential interface with a nominal swing of 200mV that retains the many benefits of the LVDS interface for a high-bandwidth, robust digital interface.
PPDS– Point to point differential signaling (PPDS) is a National Semiconductor defined signaling standard used for LCD displays that simplifies the interconnect to improve display performance, enable smaller bezels, and adding other features.
Flat Link–Flat Link is a Texas Instruments-defined LVDS-based link between a host panel and display panel in an LCD monitor and television platform. This interface is similar to that of FPD link, and is primarily used by Philips and Thomson. Cyclone III FPGAs are predominantly placed at the transmit-end of the Flat Link to meet the maximum data rate requirement of 622 Mbps and can be used on the receiver-side as well.
mini-LVDS–mini-LVDS is a Texas Instruments-defined interface similar to RSDS and meets the same needs. The requirements for mini-LVDS interfaces are identical to that of RSDS, except in the AC timing requirements. mini-LVDS assumes a center-aligned output clock.
Cyclone III FPGAs can enable you to effectively implement these protocols with features such as on-chip termination (OCT) allowing you to drive multiple signals and ease board layout and reliability.
PCI Express is rapidly establishing itself as the successor to PCI, providing higher performance, increased flexibility, and scalability for next-generation systems without increasing costs, all while maintaining software compatibility with existing PCI applications. Cyclone III FPGAs are an effective way to quickly implement a PCI Express link and take advantage of the increased scalable bandwidth it provides. You can easily design high-volume, low-cost PCI Express x1 solutions today with Cyclone III FPGAs and external PHY transceivers.
The PCI local bus is a high-performance 32-bit or 64-bit bus with multiplexed address and data lines. The bus provides a processor-independent data path between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The Cyclone III FPGA PCI system interface is designed to be compatible with the 3.3-V PCI Local Bus Specification (Rev. 2.2) and meets 64-bit/66-MHz operating frequency and timing requirements. The I/O elements in Cyclone III FPGAs are specifically designed to meet the strict PCI set-up and hold time requirements. To provide maximum flexibility, each input signal can go through two separate delay paths feeding different areas of the device.
Since the introduction of the 66-MHz PCI Local Bus Specification in 1994, bandwidth requirements of peripheral devices have grown steadily. The preferred approach to moving beyond today’s PCI Local Bus Specification is to enhance it. PCI-X enables the design of systems and devices that can operate at speeds significantly higher than today’s specification allows. Just as importantly, it provides backward compatibility by allowing devices to operate at conventional PCI frequencies and modes when installed in conventional systems. This high degree of backward compatibility enables the easy migration of systems and devices to bandwidth in excess of 1 gigabit per second (Gbps). Cyclone III FPGAs meet both the 33-MHz and the 66-MHz protocols and timing requirements of PCI and the timing requirements of PCI-X up to 100 MHz.
Table 1 lists the required PCI bus operation modes when devices of various PCI standards are used.