The Intel® High Level Synthesis Compiler Release Notes provide late-breaking information about the Intel HLS Compiler, included with the Intel Quartus® Prime software version 19.2. This document contains versions 19.2 of the Intel HLS Compiler.
The Intel HLS Compiler User Guide provides instructions on synthesizing, verifying, and simulating intellectual property (IP) that you design for Intel FPGA products. Go through the entire development flow of your component from creating your component and testbench up to integrating your component IP into a larger system with the Intel Quartus Prime software.
The Intel HLS Compiler Reference Manual provides reference information about the features supported by the Intel HLS Compiler. Find details on Intel HLS Compiler command options, header files, pragmas, attributes, macros, declarations, arguments, and template libraries.
The Intel HLS Compiler Best Practices Guide provides techniques and practices that you can apply to improve the FPGA area utilization and performance of your HLS component. Typically, you apply these best practices after you verify the functional correctness of your component.
The Intel High Level Synthesis (HLS) Accelerator Functional Unit (AFU) design example shows how to create AFUs for the Intel Acceleration Stack with the Intel HLS compiler.
Factors an input matrix into a Q matrix (which is ortho-normal) and an R matrix (which is upper triangular) using the popular Modified Gram Schmidt (MGS) algorithm. This design is runtime-parameterizable, so the size of the matrix to factor can be specified when the component is invoked. Before compiling the design, users can specify the maximum matrix size that the component can handle. It illustrates a number of HLS practices including memory banking for parallel access, streaming interfaces, and more.
In the class, you will learn how to use the Intel® HLS Compiler to synthesize, optimize, and verify design components for Intel FPGAs. We will first discuss the benefits of HLS then talk about features of the Intel HLS Compiler. You will learn how to use the compiler options, the generated reports, and the final generated files to integrate the IP within an Intel Quartus® design software project. Lastly you will learn how to effectively optimize your IP using the generated reports.
At Course Completion, you will be able to:
Use the Intel HLS Compiler to synthesize an Intel Quartus-compatible component
View reports to debug and optimize the component
Co-simulate your HLS component using an RTL simulator with a software testbench
Integrate the HLS-generated component within an FPGA design
Understand the various interfaces available and be able to select the optimal one for various types of components
Effectively use various data types and math support features
In the class, you will learn how to use advanced techniques using the Intel HLS Compiler to create an optimized IP for Intel FPGAs. We will cover using recommended techniques to improve loop pipelining performance. We will discuss how the Intel HLS compiler generates and optimizes local memory architecture as well as how to best guide the compiler to create never-stall local memories. Lastly, we will use several real-life design examples to demonstrate the optimization flow.
At course completion, you will be able to:
Use the HTML reports generated by the Intel HLS Compiler to locate performance bottlenecks in a component
Effectively pipeline loops by removing data and memory dependencies
Use pragmas to control HLS loop performance
Optimize local memory architecture
Use all the optimization tools available in the Intel HLS Compiler to create a high-performance FPGA IP