Reduce Full Design Iterations with Early Placement Stage


The incremental optimization capability in the Intel® Quartus® Prime Pro Edition software offers a fast methodology to converge to design sign-off with a new Early Placement stage.

The traditional fitter stage is divided into finer stages for more control over the flow in the Intel Quartus Prime Pro Edition software:

  • Plan stage allows legal placement and clock planning, along with timing analysis on preliminary I/O and HSSI to FPGA fabric transfers
  • Placement stage enables timing analysis before proceeding to the Route stage. The Placement stage is split into an Early Placement stage and a final placement stage:
    • Perform timing analysis after the Early Placement stage
    • Chip planner provides a visual view of the Early Placement stage
  • Route is split into Route and Post-Route stage for faster design convergence.
    • 3-corner timing analysis after route, and 4-corner timing analysis after post-route reduces compile time.
    • The post-route stage offers an Engineering Change Order (ECO)-like flow where setup and hold failures are automatically fixed, thus reduces compile time.
    • High-speed or low-power tile optimization is performed in the Post-Route stage.

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