We offer a variety of embedded training resources including online training, instructor-led courses, webcasts, tutorials, and online demonstrations to sharpen your competitive edge.
Embedded Training Resources
| Title | Description |
|---|---|
| Online Training | |
| ARM SoC FPGA | |
| SoC FPGA Hardware Overview (Part 1) | This online training describes the Cyclone® V and Arria® V SoC FPGA hardware, and in particular, the hard processor system (HPS). The online training includes information about the master programming unit (MPU) subsystem, including the ARM® Cortex™-A9 processor core, the AMBA® AXI™ bridges, the Level 3 and Level 4 interconnects, and the main memory that is included in the HPS. Course Length: 1 hour |
| SoC FPGA Hardware Overview (Part 2) | This online training describes about the Cyclone V and Arria V SoC FPGA hardware, and in particular, the HPS. The online training includes information about the peripherals included in the HPS. You will learn about system management, non-volatile storage, interface protocols, general purpose peripherals, and debugging techniques. Course Length: 30 minutes |
| Nios II Processor | |
| Developing Software for Embedded Systems on FPGAs | This online training describes how to develop software for embedded systems on FPGAs. FPGAs are becoming more common in embedded design. See how easy it is to develop embedded system software for FPGAs using the popular Nios® II soft processor. Course Length: 6 minutes |
| Developing Software for the Nios II Processor: Nios II Software Build Tools for Eclipse | This online training describes about the Nios II Software Build Tools for Eclipse, a comprehensive collection of tools for Nios II software development including compiling, editing, debugging, and flash programming. This course is an introduction on how to use these tools. Course Length: 30 minutes |
| Nios II Software Build Tools For Eclipse and BSP Editor | This online training describes about the Nios II Software Build Tools for Eclipse. You will learn how to upgrade Nios II Integrated Development Environment (IDE) projects and use the Nios II BSP Editor—a powerful feature that enables fine control over software build options. This online training was last updated for Quartus II v10.0. Course Length: 30 minutes |
| Developing Software for the Nios II Processor: HAL Primer |
This online training introduces the fundamental concepts of the Nios II Hardware Abstraction Layer (HAL) and shows the various HAL resources that are provided to accelerate software development for the Nios II processor. Course Length: 30 minutes |
Using the Nios II Processor: Hardware Development
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Learn about the Nios® II embedded soft processor v. 14.1. Learn the basics of the Avalon Standard Interface and the Qsys high performance network-on-a-programmable-chip architecture. Learn to use the Qsys system integration tool to develop & configure customized Nios II processor-based hardware systems. Utilize the associated Nios II processor and Qsys “Hello World” lab on the MAX® 10 Development kit to exercise the concepts discussed in the slides and associated tool demonstrations included in this class. Course Length: 27 minutes |
| Using the Nios II Processor: Software Development | Learn about the Nios® II Software Build Tools for Eclipse v. 14.1. Learn to develop software for FPGAs & use Nios II Development Kits for prototyping. Utilize the associated Nios II processor and Qsys “Hello World” lab on the MAX® 10 Development kit to exercise the concepts discussed in the slides and associated tool demonstrations included in this class. Course Length: 10 minutes |
| Using the Nios II Processor: Custom Components and Instructions | Learn about custom components and instructions and how to incorporate your own custom logic into a Nios® II processor based system. Course length: 11minutes |
| System Integration and Hardware Development | |
| VHDL Basics | This online training provides an overview of the VHDL language and its usage in programmable logic design. While the emphasis is on the synthesis constructs of VHDL, you will also learn about some simulation constructs. You will gain a basic understanding of VHDL that enables you to begin creating your design. Course Length: 1.5 hours |
| Instructor-Led Training | |
| Developing Software for the Nios II Processor | This training is targeted for software engineers. This training teaches you how to develop and run embedded software for the Nios II processor in the Nios II IDE. You will also be exposed to a few basic concepts including how a Nios II processor is configured and integrated into an Intel® FPGA using Quartus® II software and SOPC Builder design tools. Course Length: 2 days |
| Designing with the Nios II Processor | This training teaches you how to embed a Nios II 32-bit microprocessor soft core into your FPGA design. Learn how the software build flow is incorporated into the hardware flow, perform debug and bring up of a design, simulate your Nios II-based design in the ModelSim®-Intel FPGA software, and create custom instructions to perform hardware acceleration of software functions. This training enables you to immediately start using the Nios II processor v11.1 in your designs or on a development kit. Course Length: 1 day |
| Online Demonstrations | |
| Nios II Processor Hardware Development Flow | This online demonstration includes the following topics:
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| Nios II Software Development Flow | This online demonstration includes the following topics:
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| Programming Flash | This online demonstration shows you how the Nios II flash programmer programs data into a flash memory device connected to an FPGA. The flash programmer sends file contents over a download cable to a Nios II processor system running on the FPGA. |
| Tutorials | |
| These tutorials provide you with step-by-step instructions and walk you through simple design examples. | |
| This tutorial teaches you how to build a single design with multiple Nios II processors and run the software. | |
Using Tightly Coupled Memory with the Nios II Processor Tutorial (PDF) |
This tutorial teaches you how to boost real time system performance using tightly coupled memory with the Nios II processor to store critical code or data for low-latency access. |