Implementing Wide-Input Functions in MAX II CPLDs

For 16 and 32 inputs, MAX® II CPLD performance for wide-input, address-decode designs is comparable to MAX 7000AE devices. However, as the number of inputs increases, the MAX II performance advantage increases substantially. Unlike traditional, macrocell-based CPLD architectures that have a large quantized delay, MAX II CPLDs contain a fine-grained architecture that has a much smaller incremental delay. Table 1 shows the performance comparison between MAX II and MAX 7000AE devices.

Table 1. Performance Comparison of Wide-Input Functions

Design Type

Function Width

Best MAX II Performance (ns)

Best MAX 7000AE Performance (ns)

Address decoder with a single address

16 inputs



32 inputs



64 inputs



Although the MAX II architecture is different than the traditional CPLD architecture, the software techniques for optimizing wide-input functions (for fitting and performance) remain the same. Wide-input functions are divided into multiple levels of logic to balance fitting and performance objectives. While the MAX 7000AE architecture has more inputs per logic array block (LAB), the MAX II architecture has features that improve fitting and deliver fast performance (see Table 2).

Table 2. MAX II Features That Support Wide-Input Functions



No fixed connection between logic and I/O cells

I/O cells in conventional CPLDs are locked to specific macrocells, resulting in placement constraints. MAX II CPLDs do not have this restriction because they have a flexible connection between the logic and I/O cells. Every logic element (LE) can be routed to every I/O pin.

More logic capacity per LAB

MAX II logic blocks contain two times more logic capacity than a conventional CPLD macrocell block, enabling more logic functions to be implemented within an LAB (i.e., maintaining single-level logic) and faster performance.

Fast LAB-to-LAB delay for multi-level logic functions

Accelerates performance for multi-level logic functions, such as implementing complex wide-input functions that require two or more levels of logic.

Embedded carry chain and cascade chain

Enables a faster path from LAB-to-LAB or LE-to-LE, further accelerating design performance.


Typical wide-input applications include address decoders, state machines, and fast counters. For these applications, the fan-in is normally the width of the address bus. For functions that exceed the maximum fan-in per LAB, multiple LABs are used. In these cases, performance degradation is minimized because of the MAX II device’s minimal LAB-to-LAB delay.