Parallel Flash Loader for MAX II CPLDs

Figure 1. Using the Parallel Flash Loader to Program Non-JTAG-Compliant Discrete Flash
Figure 2. Parallel Flash Loader Implementation in MAX II CPLDs


The JTAG state machine is implemented in the hard logic of the MAX II device, and only the Parallel Flash Loader megafunction and user logic is implemented in programmable logic (see Figure 2). This implementation allows use of the JTAG state machine during normal operation of the MAX II CPLD, not just during device programming or testing.

Programming Standard Flash Memory Devices

Standard flash memory devices do not have JTAG scan connections for in-system programming. Normally, flash devices are programmed using the serial JTAG boundary scan chain of the device to which they are connected. This implementation is slow and inefficient because the programming instructions must be shifted through each I/O pin of the JTAG device one bit at a time until they reach the I/O pins connected to the flash device.

The Parallel Flash Loader megafunction and application note (AN 386: Using the MAX II Parallel Flash Loader with the Quartus® II Software (PDF)) provide a simple and efficient way to program flash devices through the MAX II device's JTAG interface. Using these tools, a special I/O scan chain can be defined to program and verify the flash device using custom commands. This implementation uses the JTAG state machine to access the MAX II device’s programmable logic to implement the flash memory driver and address decoder functions. The programming instruction is loaded directly into the flash device through the connecting I/O pins.