General-Purpose Logic

As with traditional macrocell-based CPLDs, MAX® II low-power, low-cost CPLDs can target non-applications-based, general-purpose logic solutions, ranging anywhere from ASIC and ASSP bug fixes to general-purpose timing fixes.

With the increasing cost and time associated with re-spinning ASICs and ASSPs, small bugs in the silicon need to be dealt with quickly and cost-efficiently. MAX II CPLDs provide a fast, flexible solution that can effortlessly support those eleventh-hour changes that unavoidably appear late in the design cycle, even after the board has been laid out. Table 1 describes some MAX II features that serve these general-purpose logic needs.

Table 1. MAX II CPLD Application Solutions: General-Purpose Logic

MAX II Features


Lowest Cost per I/O Pin

Keeps costs down when high I/O count requirements are needed, such as with address decoding or bus arbitration.

Fast, flexible tPD

Enables fast tPD even with multiple levels of logic, providing maximum flexibility for complex functions.


Offers programming flexibility for unexpected problems that may come up late in the design cycle.

Second Time Fitting

System design corrections often require work to perfect the design after the device is fixed on the board and the pin-out is set. MAX II CPLDs enable high-performance criteria to be met even when working with a pin-locked design.

The majority of bug fixes involve getting two devices with a fixed functionality to communicate correctly with each other. The issues are often timing-related, where one device is communicating too fast or with incompatible hand-shaking. Figure 1 shows how a low-cost MAX II CPLD can correct this problem without a costly re-spin.

Figure 1. Timing Fixes