Transceiver Signal Integrity Development Kit, Stratix V GT Edition
from Intel® (Formerly Altera)
The Altera® Stratix® V GT Transceiver Signal Integrity (SI) Development Kit provides a platform for electrical compliance testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as implemented in the system with transceiver channels available through SMA and popular backplane connectors. You can use this development kit to perform the following tasks:
Evaluate transceiver link performance up to 25.7 Gbps
Generate and check pseudo-random binary sequence (PRBS) patterns via a simple to use GUI (does not require the Quartus® Prime design software)
Access advanced equalization to fine tune link settings for optimal bit error ratio (BER)
Perform jitter analysis
Verify physical media attachment (PMA) interoperability with Stratix V GT FPGAs for targeted protocols, such as CEI-25/28G, CEI-11G, PCI Express® (PCIe®) Gen 3.0, 10GBASE-KR, 10 Gigabit Ethernet, XAUI, CEI-6G, Serial RapidIO®, HD-SDI, and others
Use the built-in high speed backplane connectors to evaluate custom backplane performance and evaluate link BER
Ordering Information
Table 1. Transceiver Signal Integrity Development Kit, Stratix V GT Edition Ordering Information
Ordering Code
Price
Ordering Information
DK-SI-5SGTMC7N
$12,995
-3 transceiver speed grade (GT data rates up to 25.7 Gbps)
In North America, call 1-888-800-0631 or contact your local distributor.
For International sales, contact your local distributor.
Buyer represents that it is a product developer, software developer or system integrator and acknowledges that this product is an evaluation kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.
Development Kit Contents
The Transceiver SI Development Kit, Stratix V GT Edition has the following features:
Stratix V GT development board (see Figure 1)
Featured device
5SGTMC7K3F40C2N
Configuration status and set-up elements
JTAG
On-board USB-BlasterTM
Fast passive parallel (FPP) configuration via MAX® II device and flash memory
Two configuration file storage
Temperature measurement circuitry (die and ambient temperature)
Quartus Prme design software includes support for Stratix V FPGAs
1-year license included
Nios® II Embedded Design Suite
MegaCore® intellectual property (IP) library includes PCIe, Triple-Speed Ethernet, serial digital interface (SDI), and DDR3 SDRAM High-Performance Controller MegaCore IP cores
IP evaluation available through OpenCore Plus
Board Update Portal
Featuring Nios II web server and remote system update
GUI-based Board Test System
Interfaces to PC via JTAG
User controllable PMA settings (pre-emphasis, equalization, and so on)
Status indication (errors, BER, and so on)
Complete documentation
User guide
Reference manual
Board schematics and layout design files
Figure 1. Stratix V GT Transceiver SI Development Kit
Table 2. Collateral for the Transceiver Development Kit, Stratix V GT Edition
Zip package of all files included in the development kit, including the reference manual, user guide, quick-start guide, BOM, layout, PCB, schematics, Board Update Portal example file, and so on.