Transceiver Signal Integrity Development Kit, Stratix V GT Edition

from Intel® (Formerly Altera)

The Altera® Stratix® V GT Transceiver Signal Integrity (SI) Development Kit provides a platform for electrical compliance testing and interoperability analysis. The accessibility to multiple channels allows for real-world analysis as implemented in the system with transceiver channels available through SMA and popular backplane connectors. You can use this development kit to perform the following tasks:

  • Evaluate transceiver link performance up to 25.7 Gbps
  • Generate and check pseudo-random binary sequence (PRBS) patterns via a simple to use GUI (does not require the Quartus® Prime design software)
  • Access advanced equalization to fine tune link settings for optimal bit error ratio (BER)
  • Perform jitter analysis
  • Verify physical media attachment (PMA) interoperability with Stratix V GT FPGAs for targeted protocols, such as CEI-25/28G, CEI-11G, PCI Express® (PCIe®) Gen 3.0, 10GBASE-KR, 10 Gigabit Ethernet, XAUI, CEI-6G, Serial RapidIO®, HD-SDI, and others
  • Use the built-in high speed backplane connectors to evaluate custom backplane performance and evaluate link BER

 

Ordering Information

Table 1. Transceiver Signal Integrity Development Kit, Stratix V GT Edition Ordering Information

Ordering Code Price Ordering Information
DK-SI-5SGTMC7N $12,995

-3 transceiver speed grade (GT data rates up to 25.7 Gbps)
In North America, call 1-888-800-0631 or contact your local distributor.
For International sales, contact your local distributor.

Buyer represents that it is a product developer, software developer or system integrator and acknowledges that this product is an evaluation kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.

Development Kit Contents

The Transceiver SI Development Kit, Stratix V GT Edition has the following features:

  • Stratix V GT development board (see Figure 1)
    • Featured device
      • 5SGTMC7K3F40C2N
    • Configuration status and set-up elements
      • JTAG
      • On-board USB-BlasterTM
      • Fast passive parallel (FPP) configuration via MAX® II device and flash memory
      • Two configuration file storage
      • Temperature measurement circuitry (die and ambient temperature)
    • Clocks
      • 50 MHz, 125 MHz, programmable oscillators (preset values: 624 MHz, 644.5 MHz, 706.25 MHz, and 875 MHz)
      • SMA connectors for supplying an external differential clock to transceiver reference clock
      • SMA connectors for supplying an external differential clock to the FPGA fabric
      • SMA connectors to output a differential clock from the FPGA's phase-locked loop (PLL) output pin
    • General user input/output
      • 10-/100-/1000-Mbps Ethernet PHY (RGMII) with RJ-45 (copper) connector
      • 16x2 character LCD
      • One 8-postion dipswitch
      • Eight user LEDs
      • Four user pushbuttons
    • Memory devices
      • 128-megabyte (MB) sync flash memory (primarily to store FPGA configurations)
    • High-speed serial interfaces
      • Four full-duplex GTB (28.05 Gbps) transceiver channels routed to MMPX connectors
      • Seven full-duplex GXB (12.5 Gbps) transceiver channels routed to SMA connectors
        • Short trace routed on a micro-strip
        • Six strip-line channels from the with all the trace lengths are matched across channels
      • 21 full-duplex GXB transceiver channels routed to backplane connector
        • Seven channels to Molex® Impact® connector
        • Seven channels to Amphenol® XCede®
        • Seven channels to footprint of Tyco Strada® Whisper® (connector is not populated)
    • Power
      • Laptop DC input
      • Voltage margining
  • Stratix V GT Transceiver SI Development Kit software content
    • Intel® FPGA's Complete Design Suite (download from Intel® FPGA download center)
      • Quartus Prme design software includes support for Stratix V FPGAs
      • 1-year license included
      • Nios® II Embedded Design Suite
      • MegaCore® intellectual property (IP) library includes PCIe, Triple-Speed Ethernet, serial digital interface (SDI), and DDR3 SDRAM High-Performance Controller MegaCore IP cores
      • IP evaluation available through OpenCore Plus
    • Board Update Portal
      • Featuring Nios II web server and remote system update
    • GUI-based Board Test System
      • Interfaces to PC via JTAG
      • User controllable PMA settings (pre-emphasis, equalization, and so on)
      • Status indication (errors, BER, and so on)
    • Complete documentation
    • User guide
    • Reference manual
    • Board schematics and layout design files

Figure 1. Stratix V GT Transceiver SI Development Kit

Table 2. Collateral for the Transceiver Development Kit, Stratix V GT Edition

Document Description Version
Transceiver Signal Integrity Development Kit, Stratix V GT Edition User Guide (PDF) Information about setting up the Transceiver SI Development Kit and using the included software. 1.1
Transceiver Signal Integrity Development Kit, Stratix V GT Edition Reference Manual (PDF) Detailed information about board components and interfaces. 1.1

Kit Files (Zip)

 Zip package of all files included in the development kit, including the reference manual, user guide, quick-start guide, BOM, layout, PCB, schematics, Board Update Portal example file, and so on. 12.1.1.0