Stratix® V DSP Development Kit
Overview
The DSP Development Kit, Stratix® V Edition provides a complete design environment that includes all the hardware and software you need to begin developing DSP-intensive FPGA designs immediately. You can use this development kit to do the following:
- Develop and test PCI Express® (PCIe®) designs at data rates up to Gen3(1) using the PCIe short card form factor-compliant development board
- Develop and test memory subsystems for DDR3 or QDR II memories
- Use the high-speed mezzanine card (HSMC) connectors to interface to one of over 35 different HSMCs provided by approved companies(2), supporting protocols such as Serial RapidIO®, 10 Gbps Ethernet, SONET, CPRI, OBSAI, and others
Ordering Information
| Ordering Code | Price | Ordering Information |
|---|---|---|
| DK-DEV-5SGSMD5N | $6,995
|
The DSP Development Kit, Stratix V Edition features a 5SGSMD5N device and a 1-year license for the Quartus® Prime design software. Buy online via the eStore or contact your local Intel® FPGA distributor to place your order. |
- Buyer represents that it is a product developer, software developer or system integrator and acknowledges that this product is an evaluation kit that is not FCC authorized, is made available solely for evaluation and software development, and may not be resold.
- You can purchase optional HSMC connector interface-compatible daughter cards, adapters, or cables to use with your development kit.
Development Kit Contents
The DSP Development Kit, Stratix V Edition features the following:
- Stratix V GS FPGA development board (see Figure 1)
- Featured device:
- Stratix V GS FPGA: 5SGSMD5K2F40C2N
- Configuration, status, and setup elements
- JTAG
- On-board USB-BlasterTM II cable
- Fast passive parallel (FPP) configuration via MAX® V device and flash memory
- One reset config push button
- One CPU reset push button
- Two configuration push buttons
- Clocks
- 50 MHz and 125 MHz programmable oscillators
- SMA input (LVPECL)
- General user input and output
- 10/100/1000Mbps Ethernet PHY (SGMII) with RJ-45 (copper) connector
- 16x2 character LCD
- One 8-position dual in-line package (DIP) switch
- Sixteen user LEDs
- Three user push buttons
- Memory devices
- DDR3 SDRAM (1,152 MB, x72 bit wide)
- QDR II+ SRAM (4.5 MB, 2 Mb x18 bit wide)
- Footprint compatible to QDR II 4 Mb x18 bit wide
- RLDRAM II (72-Mbyte CIO RLDRAM II with an 18-bit data bus)
- Component and interfaces
- PCIe x8 edge connector
- Two HSMC connectors
- SMB for serial digital interface (SDI) input and output
- QSFP optical cage
- 10/100/1000Mbps Ethernet PHY (SGMII) with RJ-45 (copper) connector
- Power
- Laptop DC input
- PCIe edge connector
- Nios® II processor web server and remote system update
- Loopback and debug HSMC cards
- Power adapter and cables
- Stratix V GS FPGA Development Kit software content
- Complete documentation
- User guide
- Reference manual
- Board schematics and layout design files
- GUI-based Board Test System
- Includes complete Intel Quartus Prime design software projects with open source RTL
- Board Update Portal
- Includes complete Intel Quartus Prime design software projects with open source RTL
- Intel Quartus Prime design software, Development Kit Edition (DKE)
- License to use full version of Intel Quartus Prime design software for one year
- Complete documentation
- Featured device:
Table 2. Collateral
| Kit Name (Ordering Code) |
Document | Description | Version |
|---|---|---|---|
DSP Development Kit, Stratix V Edition (DK-DEV-5SGSMD5N) |
DSP Development Kit, Stratix V Edition FPGA Development Board Reference Manual (PDF) | Detailed information about board components and interfaces. | 12.0 |
| DSP Development Kit, Stratix V Edition User Guide (PDF) | Information about setting up the Stratix V GS FPGA development board and using the included software. | 12.0 | |
| Kit installation | Full installation of all files including: reference manual, user guide, quick-start guide, BOM, layout, PCB, schematics, Board Update Portal example file, Board Test System example file, and others | 12.0 |