MAX IIZ CPLD Demonstration Board

Intel's new zero-power MAX® IIZ devices are the lowest power CPLDs now shipping in the industry. The MAX IIZ demonstration board shows the EPM240Z device's low power capability and highlights several common uses for CPLDs. Contact your local Intel® sales representative to arrange a demonstration.

Value of CPLDs

CPLDs provide a fast, inexpensive low-risk method to customize ASSP chipsets. You can use CPLDs to create new functions or enhance existing functions. Common functions implemented inside CPLDs are:

  • Level shifting
  • I/O expansion
  • Peripheral replacement
  • Flash memory interfaces
  • Interrupt handling
  • Power sequencing
  • Battery gauges
  • Keyboard/touchscreen decoders

Power Consumption Measurement and Design Example

The demonstration board comes with a pre-loaded design example. The functional design is a “clock,” displaying the time of day. You can take power measurements of the CPLD when operating this design example in four modes of system operation. Table 1 describes the system and CPLD conditions for these common system modes.

Table 1. MAX IIZ Demonstration Board—Design Example, System Modes, and Relative Power

Design Example System Mode Description System Conditions CPLD Conditions
Power Mode I/O Switching I/O Toggle Rate Device On/Off Oscillator Input I/Os Driving CPLD Power Consumption
Clock display "on" High-Speed User Operation Dynamic Yes Any On On (1) Yes Mostly dynamic, some static
Clock display "on" Low-Speed User Operation Dynamic Yes Any On On (2) Yes Dynamic and static
Clock display "on" Standby Standby No N/A On Off No Static (ICCSTANDBY)
Off Off Off Either N/A Off Either No Leakage (IDK)


  1. You must supply an external clock source and recompile the design to connect the external clock source through one of the 10-pin headers to the internal logic.
  2. 32 kHz, supplied by the on-board oscillator.

There are three power measurement options on the MAX IIZ CPLD demonstration board. You can probe the following nodes with a portable multi-meter:

  • MAX IIZ CPLD, device core only (demonstration boards are averaging ~20-µA standby ICC )
  • MAX IIZ CPLD, I/O bank 1
  • MAX IIZ CPLD, I/O bank 2

High speed is typically defined as a system clock running at 20 MHz or faster. MAX IIZ CPLDs have on average 50 percent lower dynamic power versus competing CPLDs. Since dynamic power is dependent on the system clock, using MAX IIZ CPLDs result in the lowest power for high-speed applications. Low speed is defined as less than 10 MHz, but is typically in the kHz range.

One of the best techniques for lowering system power consumption is to selectively turn off components when they are not being used. MAX IIZ devices are the only CPLDs with an internal oscillator, allowing the device to automatically power off. For the "clock" design example, the internal oscillator is used as part of the capacitive push-button functionality (i.e., to set the hours/minutes digits on the display or reset the display).

Another related theme is using a CPLD as a low-power coprocessor. This webcast shows how adding a CPLD to your design can actually lower total system power 50x to 100x by offloading simple system tasks from a power-hungry embedded processor or ASSP to a power-frugal MAX IIZ CPLD.


Board Details

  • User interface
    • Four digit, seven-segment LCD
    • Eight bi-color LEDs
    • Six capacitive buttons
  • Clocking
    • External 32.768-kHz oscillator
  • Connectors
    • 2 x 5 male 0.1” pitch header
    • 2 x 5 female 0.1” pitch header
  • Power
    • Coin cell battery or two AAA batteries
    • Brownout protection
    • Adjustable I/O voltage
  • CPLD configuration
    • Via on-board JTAG header (download cable required)
  • Download board schematic, BOM and Quartus® II files (via FTP site)
    • Contact your local Altera FAE for additional board documentation
Figure 1. MAX IIZ Demonstration Board

Perform the following steps to turn on the MAX IIZ demonstration board:

  1. Press and hold the PWR_PB button for five seconds to power up board and enable design example.
  2. Press and hold button PB4 to change the displayed time. Buttons PB1 and PB2 increment/decrement the hour digits, while buttons PB2 and PB6 increment/decrement the minutes digits.
  3. Press button PB5 to reset the clock to 12:00.