Intel's new zero-power MAX® IIZ devices are the lowest power CPLDs now shipping in the industry. The MAX IIZ demonstration board shows the EPM240Z device's low power capability and highlights several common uses for CPLDs. Contact your local Intel® sales representative to arrange a demonstration.
CPLDs provide a fast, inexpensive low-risk method to customize ASSP chipsets. You can use CPLDs to create new functions or enhance existing functions. Common functions implemented inside CPLDs are:
Flash memory interfaces
Power Consumption Measurement and Design Example
The demonstration board comes with a pre-loaded design example. The functional design is a “clock,” displaying the time of day. You can take power measurements of the CPLD when operating this design example in four modes of system operation. Table 1 describes the system and CPLD conditions for these common system modes.
Table 1. MAX IIZ Demonstration Board—Design Example, System Modes, and Relative Power
You must supply an external clock source and recompile the design to connect the external clock source through one of the 10-pin headers to the internal logic.
32 kHz, supplied by the on-board oscillator.
There are three power measurement options on the MAX IIZ CPLD demonstration board. You can probe the following nodes with a portable multi-meter:
MAX IIZ CPLD, device core only (demonstration boards are averaging ~20-µA standby ICC )
MAX IIZ CPLD, I/O bank 1
MAX IIZ CPLD, I/O bank 2
High speed is typically defined as a system clock running at 20 MHz or faster. MAX IIZ CPLDs have on average 50 percent lower dynamic power versus competing CPLDs. Since dynamic power is dependent on the system clock, using MAX IIZ CPLDs result in the lowest power for high-speed applications. Low speed is defined as less than 10 MHz, but is typically in the kHz range.
One of the best techniques for lowering system power consumption is to selectively turn off components when they are not being used. MAX IIZ devices are the only CPLDs with an internal oscillator, allowing the device to automatically power off. For the "clock" design example, the internal oscillator is used as part of the capacitive push-button functionality (i.e., to set the hours/minutes digits on the display or reset the display).
For information on implementing the capacitive push-buttons, contact your local Intel sales representative (or view a related article).
Another related theme is using a CPLD as a low-power coprocessor. This webcast shows how adding a CPLD to your design can actually lower total system power 50x to 100x by offloading simple system tasks from a power-hungry embedded processor or ASSP to a power-frugal MAX IIZ CPLD.
MAX IIZ EPM240ZM100C7N CPLD
Four digit, seven-segment LCD
Eight bi-color LEDs
Six capacitive buttons
External 32.768-kHz oscillator
2 x 5 male 0.1” pitch header
2 x 5 female 0.1” pitch header
Coin cell battery or two AAA batteries
Adjustable I/O voltage
Via on-board JTAG header (download cable required)