FPGA Designer

FPGA designers can now develop accelerator functions using any hardware description language (HDL) (e.g. Verilog/VHDL). A great way to get started is to simply select a platform and use the provided FPGA Interface Manager to seamlessly integrate your accelerator function with the software framework and applications on Intel® Xeon® CPUs. 

 

Note: For access to the Intel® FPGA Programmable Acceleration Card with D5005 Platform Qualification Guidelines, please contact an Intel representative.

 

Software Developer

Software developers can make use of the Open Programmable Acceleration Engine (OPAE) software programming layer to develop libraries, frameworks, and applications that call accelerator functions that are implemented in FPGA hardware.

Training

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. 

Archived versions will be available as new Intel® Acceleration Stacks for the Intel® FPGA PAC D5005 are introduced.

Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 2.0 Resources

Find technical documentation for your Intel® Acceleration Stack Version 2.0.