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PCI_MSI_CAP_ID_NEXT_CTRL_REG
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0x0 |
DisplayName: MSI Capability Header and Message Control Register.
Register Size: 32
Value After Reset: 0x1807005
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This register holds MSI Capability Header information and controls the MSI behaviour. |
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MSI_CAP_OFF_04H_REG
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0x4 |
DisplayName: Message Address Register for MSI (Offset 04h).
Register Size: 32
Value After Reset: 0x0
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This register holds the system specified message address for an MSI transaction. |
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MSI_CAP_OFF_08H_REG
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0x8 |
DisplayName: Message Address Register for MSI (Offset 08h).
Register Size: 32
Value After Reset: 0x0
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For a function that supports a 32-bit message address,
- bits[31:16] of this register represent the Extended Message Data, and
- bits[15:0] of this register represent the Message Data
For a function that supports a 64-bit message address (bit 23 in PCI_MSI_CAP_ID_NEXT_CTRL_REG register set), this register represents the Message Upper Address Register for MSI (Offset 08h). It specifies the Message Upper Address (System-specified message upper address). This register is required for PCI Express Endpoints and is optional for other function types. If the Message Enable bit (bit 0 of the Message Control register) is set, the contents of this register (if non-zero) specify the upper 32-bits of a 64-bit message address (Address[63:32]). If the contents of this register are zero, the Function uses the 32 bit address specified by the Message Address register.
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MSI_CAP_OFF_0CH_REG
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0xc |
DisplayName: Message Address Register for MSI (Offset 0Ch).
Register Size: 32
Value After Reset: 0x0
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For a function that supports a 32-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.
For a function that supports a 64-bit message address, this register contains Message Data.
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MSI_CAP_OFF_10H_REG
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0x10 |
DisplayName: Message Address Register for MSI (Offset 10h).
Register Size: 32
Value After Reset: 0x0
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For a function that supports a 32-bit message address, this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.
For a function that supports a 64-bit message address, this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set.
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MSI_CAP_OFF_14H_REG
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0x14 |
DisplayName: Message Address Register for MSI (Offset 14h).
Register Size: 32
Value After Reset: 0x0
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Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. |