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PL16G_EXT_CAP_HDR_REG
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0x0 |
DisplayName: Physical Layer 16.0 GT/s Extended Capability Header.
Register Size: 32
Value After Reset: 0x1e410026
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Physical Layer 16.0 GT/s Extended Capability Header provides information about Capability ID, Version, and next offset. |
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PL16G_CAPABILITY_REG
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0x4 |
DisplayName: 16.0 GT/s Capabilities Register.
Register Size: 32
Value After Reset: 0x0
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This register is reserved for the future update. |
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PL16G_CONTROL_REG
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0x8 |
DisplayName: 16.0 GT/s Control Register.
Register Size: 32
Value After Reset: 0x0
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This register is reserved for the future update. |
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PL16G_STATUS_REG
|
0xc |
DisplayName: 16.0 GT/s Status Register.
Register Size: 32
Value After Reset: 0x0
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16.0 GT/s Status Register provides status of equalization of 16.0 GT/s speed. |
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PL16G_LC_DPAR_STATUS_REG
|
0x10 |
DisplayName: 16.0 GT/s Local Data Parity Mismatch Status Register.
Register Size: 32
Value After Reset: 0x0
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The Local Data Parity Mismatch Status register is a 32-bit vector where each bit indicates if the local receiver detected a Data Parity mismatch on the Lane with the corresponding Lane number.
This Lane number is the default Lane number which is invariant to Link width and Lane reversal negotiation that occurs during Link training. |
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PL16G_FIRST_RETIMER_DPAR_STATUS_REG
|
0x14 |
DisplayName: 16.0 GT/s First Retimer Data Parity Mismatch Status Register.
Register Size: 32
Value After Reset: 0x0
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The First Retimer Data Parity Status register is a 32-bit vector where each bit indicates if the first Retimer of a Path detected a Data Parity mismatch on the Lane with the corresponding Lane number.
This Lane number is the default Lane number which is invariant to Link width and Lane reversal negotiation that occurs during Link training. |
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PL16G_SECOND_RETIMER_DPAR_STATUS_REG
|
0x18 |
DisplayName: 16.0 GT/s Second Retimer Data Parity Mismatch Status Register.
Register Size: 32
Value After Reset: 0x0
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The Second Retimer Data Parity Status register is a 32-bit vector where each bit indicates if the second Retimer of a Path detected a Data Parity mismatch on the Lane with the corresponding Lane number.
This Lane number is the default Lane number which is invariant to Link width and Lane reversal negotiation that occurs during Link training. |
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PL16G_CAP_OFF_20H_REG
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0x20 |
DisplayName: 16.0 GT/s Lane Equalization Control Register for Lane 0-3.
Register Size: 32
Value After Reset: 0x40404040
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This Equalization Control register consists of control fields required for Lane 0-3 16.0 GT/s equalization. |
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PL16G_CAP_OFF_24H_REG
|
0x24 |
DisplayName: 16.0 GT/s Lane Equalization Control Register for Lane 4-7.
Register Size: 32
Value After Reset: 0x40404040
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This Equalization Control register consists of control fields required for Lane 4-7 16.0 GT/s equalization. |
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PL16G_CAP_OFF_28H_REG
|
0x28 |
DisplayName: 16.0 GT/s Lane Equalization Control Register for Lane 8-11.
Register Size: 32
Value After Reset: 0x40404040
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This Equalization Control register consists of control fields required for Lane 8-11 16.0 GT/s equalization. |
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PL16G_CAP_OFF_2CH_REG
|
0x2c |
DisplayName: 16.0 GT/s Lane Equalization Control Register for Lane 12-15.
Register Size: 32
Value After Reset: 0x40404040
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This Equalization Control register consists of control fields required for Lane 12-15 16.0 GT/s equalization. |