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TPH_EXT_CAP_HDR_REG
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0x0 |
DisplayName: TPH Extended Capability Header.
Register Size: 32
Value After Reset: 0x32810017
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This register provides Capability Id, Capability Revision, and Next offset of structure Extended Capability Register. |
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TPH_REQ_CAP_REG_REG
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0x4 |
DisplayName: TPH Requester Capability Register.
Register Size: 32
Value After Reset: 0x1
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This register gives information about No ST mode support, Intrrupt Vector mode, Device specific mode, Extended TPH requester support, ST table location and size.
SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a
DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register. |
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TPH_REQ_CONTROL_REG_REG
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0x8 |
DisplayName: TPH Requester Control Register.
Register Size: 32
Value After Reset: 0x0
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This register provides ST Mode Select and controls TPH Requester Enable. |
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TPH_ST_TABLE_REG_0
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0xc |
DisplayName: TPH ST Table Register 0.
Register Size: 32
Value After Reset: 0x0
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The TPH ST Table 0 must be implemented in the TPH Requester Extended Capability structure if the value of the ST Table Location field is 01b. For all other values, the ST Entry registers must not be implemented.
Each implemented ST Entry is 16 bits. The number of ST Entry registers implemented must be equal to the number of ST Table entries supported by the Function, which is the value of the ST Table Size field plus one. |