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AER_EXT_CAP_HDR_OFF
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0x0 |
DisplayName: Advanced Error Reporting Extended Capability Header.
Register Size: 32
Value After Reset: 0x14820001
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Advanced Error Reporting Extended Capability Header provides information about Capability ID, Version, and next offset. |
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UNCORR_ERR_STATUS_OFF
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0x4 |
DisplayName: Uncorrectable Error Status Register.
Register Size: 32
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The Uncorrectable Error Status Register (Offset 04h) indicates error detection status of individual errors on a PCI Express device Function.
An individual error status bit that is Set indicates that a particular error was detected; software may clear an error status by writing a 1b to the respective bit.
Register bits not implemented by the Function are hardwired to 0b. |
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UNCORR_ERR_MASK_OFF
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0x8 |
DisplayName: Uncorrectable Error Mask Register.
Register Size: 32
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The Uncorrectable Error Mask Register controls reporting of individual errors by the device Function to the PCI Express Root Complex through a PCI Express error Message.
A masked error (respective bit Set in the mask register) is not recorded or reported in the Header Log, TLP Prefix Log, or First Error Pointer, and is not reported to the PCI Express Root Complex by this Function.
There is a mask bit per error bit of the Uncorrectable Error Status register. Register fields for bits not implemented by the Function are hardwired to 0b. |
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UNCORR_ERR_SEV_OFF
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0xc |
DisplayName: Uncorrectable Error Severity Register.
Register Size: 32
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The Uncorrectable Error Severity Register controls whether an individual error is reported as a Non-fatal or Fatal error.
An error is reported as fatal when the corresponding error bit in the severity register is Set. If the bit is Clear, the corresponding error is considered non-fatal. |
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CORR_ERR_STATUS_OFF
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0x10 |
DisplayName: Correctable Error Status Register.
Register Size: 32
Value After Reset: 0x0
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The Correctable Error Status register reports error status of individual correctable error sources on a PCI Express device Function.
When an individual error status bit is Set, it indicates that a particular error occurred; software may clear an error status by writing a 1b to the respective bit.
Register bits not implemented by the Function are hardwired to 0b by the controller. |
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CORR_ERR_MASK_OFF
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0x14 |
DisplayName: Correctable Error Mask Register.
Register Size: 32
Value After Reset: 0xe000
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The Correctable Error Mask Register controls reporting of individual correctable errors by this Function to the PCI Express Root Complex through a PCI Express error Message.
A masked error (respective bit Set in the mask register) is not reported to the PCI Express Root Complex by this Function.
There is a mask bit per error bit in the Correctable Error Status register. Register fields for bits not implemented by the Function are hardwired to 0b by the controller. |
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ADV_ERR_CAP_CTRL_OFF
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0x18 |
DisplayName: Advanced Error Capabilities and Control Register.
Register Size: 32
Value After Reset: 0xa0
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Advanced Error Capabilities and Control Register provides information whether the individual capability is supported or not. If the capability is supported then it is enabled or not. |
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HDR_LOG_0_OFF
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0x1c |
DisplayName: Header Log Register 0.
Register Size: 32
Value After Reset: 0x0
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The Header Log Register 0 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 0, byte 1 of the header is in byte 2 of the Header Log Register 0, and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information. |
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HDR_LOG_1_OFF
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0x20 |
DisplayName: Header Log Register 1.
Register Size: 32
Value After Reset: 0x0
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The Header Log Register 1 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 1, byte 1 of the header is in byte 2 of the Header Log Register 1 and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information. |
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HDR_LOG_2_OFF
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0x24 |
DisplayName: Header Log Register 2.
Register Size: 32
Value After Reset: 0x0
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The Header Log Register 2 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 2, byte 1 of the header is in byte 2 of the Header Log Register 2 and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information. |
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HDR_LOG_3_OFF
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0x28 |
DisplayName: Header Log Register 3.
Register Size: 32
Value After Reset: 0x0
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The Header Log Register 3 contains the header for the TLP corresponding to a detected error; The header is captured such that, when read using DW accesses, the fields of the header are laid out in the same way the headers are presented in the specification.
Therefore, byte 0 of the header is located in byte 3 of the Header Log Register 3, byte 1 of the header is in byte 2 of the Header Log Register 3 and so forth. For 12-byte headers, only bytes 0 through 11 of the Header Log Register are used and values in bytes 12 through 15 are undefined.
In certain cases where a Malformed TLP is reported, the Header Log Register may contain TLP Prefix information. |
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TLP_PREFIX_LOG_1_OFF
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0x38 |
DisplayName: TLP Prefix Log Register 1.
Register Size: 32
Value After Reset: 0x0
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The First TLP Prefix Log Register contains the first End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented. |
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TLP_PREFIX_LOG_2_OFF
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0x3c |
DisplayName: TLP Prefix Log Register 2.
Register Size: 32
Value After Reset: 0x0
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The Second TLP Prefix Log Register contains the second End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented. |
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TLP_PREFIX_LOG_3_OFF
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0x40 |
DisplayName: TLP Prefix Log Register 3.
Register Size: 32
Value After Reset: 0x0
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The Third TLP Prefix Log Register contains the third End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented. |
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TLP_PREFIX_LOG_4_OFF
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0x44 |
DisplayName: TLP Prefix Log Register 4.
Register Size: 32
Value After Reset: 0x0
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The Fourth TLP Prefix Log Register contains the fourth End-End TLP Prefix from the TLP corresponding to the detected error. The TLP Prefix Log Register is only meaningful when the TLP Prefix Log Present bit is Set.
The TLP Prefixes are captured such that, when read using DW accesses, the fields of the TLP Prefix are laid out in the same way the fields of the TLP Prefix are described.
Therefore, byte 0 of a TLP Prefix is located in byte 3 of the associated TLP Prefix Log Register; byte 1 of a TLP Prefix is located in byte 2; and so forth. The TLP Prefix Log Registers beyond the number supported by the Function are hardwired to zero by controller.
If the End-End TLP Prefix Supported bit is Clear, the TLP Prefix Log Register is not required to be implemented. |