Registers for SRIOV_CAP

Register Name	Address Offset	Attributes	Description
SRIOV_BASE_REG	0x0	DisplayName: SR-IOV Capability Header Register. Register Size: 32 Value After Reset: 0x29c10010	SR-IOV Extended Capability Header provides information about Capability ID, Version, and Next Offset.
CAPABILITIES_REG	0x4	DisplayName: SR-IOV Capability Register. Register Size: 32 Value After Reset: 0x6	This Register provides Capability present in SR-IOV.
STATUS_CONTROL_REG	0x8	DisplayName: SR-IOV Control and Status Register. Register Size: 32 Value After Reset: 0x0	This Register provides status and control of capability.
TOTAL_VFS_INITIAL_VFS_REG	0xc	DisplayName: TotalVFs InitialVFs Register. Register Size: 32 Value After Reset: 0x1000100	This Register provides value of TotalVFs and InitialVFs.
SRIOV_NUM_VFS	0x10	DisplayName: NumVFs and Function Dependency Link Register. Register Size: 32 Value After Reset: 0x0	This Register contains value of NumVFs and Functional Dependency Link. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the controller when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
SRIOV_VF_OFFSET_POSITION	0x14	DisplayName: VF Stride and Offset Register. Register Size: 32 Value After Reset: 0x1000100 Reset Mask: 0x0	This Register contains value of VF Stride and First VFs Offset.
VF_DEVICE_ID_REG	0x18	DisplayName: VF Device ID Register Register Size: 32 Value After Reset: 0x11720000	VF Device ID may be different from the PF Device ID. A VF Device ID must be managed by the vendor. The vendor must ensure that the chosen VF Device ID does not result in the use of an incompatible device driver.
SUP_PAGE_SIZES_REG	0x1c	DisplayName: Supported Page Sizes. Register Size: 32 Value After Reset: 0x553	This Register provides the page sizes supported by the PF. This PF supports a page size of 2^(n+12), if bit n is Set. For example, if bit 0 is Set, the PF supports 4-KB page sizes.
SYSTEM_PAGE_SIZE_REG	0x20	DisplayName: System Page Size. Register Size: 32 Value After Reset: 0x1	This Register provides the page size the system will use to map the VFs' memory addresses.
SRIOV_BAR0_REG	0x24	DisplayName: VF BAR0. Register Size: 32 Value After Reset: 0x0	This register is used to define the BAR0 contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the controller from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
SRIOV_BAR1_REG	0x28	DisplayName: VF BAR1. Register Size: 32 Value After Reset: 0x0	This register is used to define the BAR1 contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the controller from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
SRIOV_BAR2_REG	0x2c	DisplayName: VF BAR2. Register Size: 32 Value After Reset: 0x0	This register is used to define the BAR2 contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the controller from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
SRIOV_BAR3_REG	0x30	DisplayName: VF BAR3. Register Size: 32 Value After Reset: 0x0	This register is used to define the BAR3 contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the controller from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
SRIOV_BAR4_REG	0x34	DisplayName: VF BAR4. Register Size: 32 Value After Reset: 0x0	This register is used to define the BAR4 contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the controller from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
SRIOV_BAR5_REG	0x38	DisplayName: VF BAR5. Register Size: 32 Value After Reset: 0x0	This register is used to define the BAR5 contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the controller from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.
VF_MIGRATION_STATE_ARRAY_REG	0x3c	DisplayName: VF Migration State Array Offset Register. Register Size: 32 Value After Reset: 0x0	If VF Migration Capable is Set and TotalVFs is not zero, this register shall contain a PF BAR relative pointer to the VF Migration State Array. This register is RO Zero if VF Migration Capable is Clear.