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SPCIE_CAP_HEADER_REG
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0x0 |
DisplayName: SPCIE Capability Header.
Register Size: 32
Value After Reset: 0x1b410019
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This Register provides Capability Id, Capability Version, and next Offset of SPCIE Structure. |
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LINK_CONTROL3_REG
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0x4 |
DisplayName: Link Control 3 Register.
Register Size: 32
Value After Reset: 0x0
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This Register controls equilization and equilization interrupt. |
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LANE_ERR_STATUS_REG
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0x8 |
DisplayName: Lane Error Status Register.
Register Size: 32
Value After Reset: 0x0
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This Register contains Lane Error Status Bits per Lane. |
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SPCIE_CAP_OFF_0CH_REG
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0xc |
DisplayName: Lane Equalization Control Register for lanes 1 and 0.
Register Size: 32
Value After Reset: 0x74007400
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This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |
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SPCIE_CAP_OFF_10H_REG
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0x10 |
DisplayName: Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) 2.
Register Size: 32
Value After Reset: 0x74007400
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The function of this register is dependent on your actual configuration.
- Gen3: LEC or RSVD depending on the value of CX_NL.
- Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |
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SPCIE_CAP_OFF_14H_REG
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0x14 |
DisplayName: Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) 4.
Register Size: 32
Value After Reset: 0x74007400
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The function of this register is dependent on your actual configuration.
- Gen3: LEC or RSVD depending on the value of CX_NL.
- Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |
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SPCIE_CAP_OFF_18H_REG
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0x18 |
DisplayName: Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) 6.
Register Size: 32
Value After Reset: 0x74007400
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The function of this register is dependent on your actual configuration.
- Gen3: LEC or RSVD depending on the value of CX_NL.
- Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |
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SPCIE_CAP_OFF_1CH_REG
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0x1c |
DisplayName: Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) 8.
Register Size: 32
Value After Reset: 0x74007400
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The function of this register is dependent on your actual configuration.
- Gen3: LEC or RSVD depending on the value of CX_NL.
- Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |
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SPCIE_CAP_OFF_20H_REG
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0x20 |
DisplayName: Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) 10.
Register Size: 32
Value After Reset: 0x74007400
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The function of this register is dependent on your actual configuration.
- Gen3: LEC or RSVD depending on the value of CX_NL.
- Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |
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SPCIE_CAP_OFF_24H_REG
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0x24 |
DisplayName: Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) 12.
Register Size: 32
Value After Reset: 0x74007400
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The function of this register is dependent on your actual configuration.
- Gen3: LEC or RSVD depending on the value of CX_NL.
- Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |
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SPCIE_CAP_OFF_28H_REG
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0x28 |
DisplayName: Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) 14.
Register Size: 32
Value After Reset: 0x74007400
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The function of this register is dependent on your actual configuration.
- Gen3: LEC or RSVD depending on the value of CX_NL.
- Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL.
This register provides Transmitter Preset and Receiver Preset Hint for Downstream Port and Upstream Port. |