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DEVICE_ID_VENDOR_ID_REG
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0x0 |
DisplayName: Device ID and Vendor ID Register.
Register Size: 32
Value After Reset: 0x11728086
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This register holds the device ID and vendor ID. |
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STATUS_COMMAND_REG
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0x4 |
DisplayName: Status and Command Register.
Register Size: 32
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This register provides the status and controls the behavior of a function. |
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CLASS_CODE_REVISION_ID
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0x8 |
DisplayName: Class Code and Revision ID Register.
Register Size: 32
Value After Reset: 0x1
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This register specifies the class code and revision ID of a function. |
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BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG
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0xc |
DisplayName: BIST, Header Type, Latency Timer, and Cache Line Size Register.
Register Size: 32
Value After Reset: 0x800000
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This register provides the status and controls BIST. It also holds information regarding the header layout, latency timer, and cache line size. |
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BAR0_REG
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0x10 |
DisplayName: BAR0 Register.
Register Size: 32
Value After Reset: 0x0
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System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM). |
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BAR1_REG
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0x14 |
DisplayName: BAR1 Register.
Register Size: 32
Value After Reset: 0x0
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System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM). |
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BAR2_REG
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0x18 |
DisplayName: BAR2 Register.
Register Size: 32
Value After Reset: 0x0
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System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM). |
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BAR3_REG
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0x1c |
DisplayName: BAR3 Register.
Register Size: 32
Value After Reset: 0x0
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System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM). |
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BAR4_REG
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0x20 |
DisplayName: BAR4 Register.
Register Size: 32
Value After Reset: 0x0
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System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM). |
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BAR5_REG
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0x24 |
DisplayName: BAR5 Register.
Register Size: 32
Value After Reset: 0x0
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System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system, and how much address space the Functions in the system require. After determining this information, system software can map the Functions into reasonable locations and proceed with system boot. In order to do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of Configuration Space. It is strongly recommended that power-up firmware/software also support the optional Enhanced Configuration Access Mechanism (ECAM). |
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CARDBUS_CIS_PTR_REG
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0x28 |
DisplayName: CardBus CIS Pointer Register.
Register Size: 32
Value After Reset: 0x0
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This register holds the CardBus CIS pointer. |
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SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG
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0x2c |
DisplayName: Subsystem ID and Subsystem Vendor ID Register.
Register Size: 32
Value After Reset: 0x0
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These registers are used to uniquely identify the add-in card or subsystem where the PCI Express component resides. They provide a mechanism for vendors to distinguish their products from one another even though the assemblies may have the same PCI Express component on them (and, therefore, the same Vendor ID and Device ID). |
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EXP_ROM_BASE_ADDR_REG
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0x30 |
DisplayName: Expansion ROM BAR Register.
Register Size: 32
Value After Reset: 0x0
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This register handles the base address and size information for this expansion ROM. |
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PCI_CAP_PTR_REG
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0x34 |
DisplayName: Capabilities Pointer Register.
Register Size: 32
Value After Reset: 0x40
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This register is used to point to a linked list of capabilities implemented by a Function. |
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MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG
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0x3c |
DisplayName: Max_Lat, Min_Gnt, Interrupt Pin, and Interrupt Line Register.
Register Size: 32
Value After Reset: 0x1ff
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The Interrupt Line register communicates interrupt line routing information. The Interrupt Pin register identifies the legacy interrupt Message(s) the Function uses. |