SMMU_CB5_TCR2

         The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA025010

Size: 32

Offset: 0x25010

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

NSCFG1

RW 0x0

Reserved

SEP

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEP

RW 0x0

NSCFG0

RW 0x0

Reserved

TBI1

RO 0x1

TBI0

RO 0x1

AS

RW 0x0

Reserved

PASize

RW 0x0