nand_bootstrap 

         Bootstrap fields sampled by NAND Flash Controller when released from reset.
All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD12030

Size: 32

Offset: 0x30

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

page512_x16

RW 0x0

Reserved

page512

RW 0x0

Reserved

tworowaddr

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

noloadb0p0

RW 0x0

Reserved

noinit

RW 0x0

nand_bootstrap Fields

Bit Name Description Access Reset
28 page512_x16 
Reset value - 0
Field name: PAGE512_x16_DEVICE
Description: If 1, NAND device has 512 bytes page size and I/O width is 16 bits. This start should be asserted in case of 512 bytes devices only. This signal must be stable and have proper value by the time Controller comes out of Reset
 RW 0x0
24 page512 
If 1, NAND device has a 512 byte page size.
 RW 0x0
16 tworowaddr 
If 1, NAND device requires only 2 row address cycles instead of the normal 3 row address cycles.
 RW 0x0
8 noloadb0p0 
If 1, inhibits NAND Flash Controller from loading page 0 of block 0 of the NAND device as part of the initialization procedure.
 RW 0x0
0 noinit 
If 1, inhibits NAND Flash Controller from performing initialization when coming out of reset. Instead, software must program all registers pertaining to device parameters like page size, width, etc.
 RW 0x0