nand_l3master 

         Controls the L3 master ARCACHE and AWCACHE AXI signals.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD12000 0xFFD12034

Size: 32

Offset: 0x34

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

arprot

RW 0x0

Reserved

awprot

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ardomain

RW 0x3

Reserved

awdomain

RW 0x3

awcache_0

RW 0x0

arcache_0

RW 0x0

nand_l3master Fields

Bit Name Description Access Reset
22:20 arprot 
ar prot register
 RW 0x0
18:16 awprot 
aw prot register
 RW 0x0
13:12 ardomain 
ar domain register
 RW 0x3
9:8 awdomain 
aw domain register
 RW 0x3
7:4 awcache_0 
Specifies the value of the module AWCACHE signal.
Value Description
0 Noncache_Nonbuff
1 Buff
2 Cache_Nonalloc
3 Cache_Buff_Nonalloc
4 Reserved1
5 Reserved2
6 Cache_Wrthru_Rdalloc
7 Cache_Wrback_Rdalloc
8 Reserved3
9 Reserved4
10 Cache_Wrthru_Wralloc
11 Cache_Wrback_Wralloc
12 Reserved5
13 Reserved6
14 Cache_Wrthru_Alloc
15 Cache_Wrback_Alloc
RW 0x0
3:0 arcache_0 
Specifies the value of the module ARCACHE signal.
Value Description
0 Noncache_Nonbuff
1 Buff
2 Cache_Nonalloc
3 Cache_Buff_Nonalloc
4 Reserved1
5 Reserved2
6 Cache_Wrthru_Rdalloc
7 Cache_Wrback_Rdalloc
8 Reserved3
9 Reserved4
10 Cache_Wrthru_Wralloc
11 Cache_Wrback_Wralloc
12 Reserved5
13 Reserved6
14 Cache_Wrthru_Alloc
15 Cache_Wrback_Alloc
RW 0x0