SMMU_ITCTRL

         This register enables the component to switch from functional mode to integration mode. You can directly control the inputs and outputs in integration mode.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA002000

Size: 32

Offset: 0x2000

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

tbu_index

RW 0x0

MODULE

RW 0x0

RAM_DATA

RW 0x0

RAM_MODE

RW 0x0

INTGMODE

RW 0x0