ddr_T_main_Probe_Filters_3_Status

         Register Status is 2-bit register that selects candidate packets based on packet status.
      
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_ddr_T_main_Probe 0xF8000000 0xF8000118

Size: 32

Offset: 0x118

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

RSPEN

RW 0x0

REQEN

RW 0x0

ddr_T_main_Probe_Filters_3_Status Fields

Bit Name Description Access Reset
1 RSPEN
Selects RSP and FAIL-CONT status packets.
RW 0x0
0 REQEN
Selects REQ status packets.
RW 0x0