MCR

         Modem Control Register
      
Module Instance Base Address Register Address
i_uart_uart_address_block 0xFF8D0000 0xFF8D0010

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_MCR_31to7

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_MCR_31to7

RO 0x0

SIRE

RO 0x0

AFCE

RW 0x0

LoopBack

RW 0x0

OUT2

RW 0x0

OUT1

RW 0x0

RTS

RW 0x0

DTR

RW 0x0

MCR Fields

Bit Name Description Access Reset
31:7 RSVD_MCR_31to7
Reserved bits [31:7] - Read Only
RO 0x0
6 SIRE
SIR Mode Enable.
Writeable only when SIR_MODE == Enabled, always readable.  This is used to enable/
disable the IrDA SIR Mode features as described in section 5.2 on page 47.
0 = IrDA SIR Mode disabled
1 = IrDA SIR Mode enabled
Value Description
0x0 IrDA SIR Mode disabled
0x1 IrDA SIR Mode enabled
RO 0x0
5 AFCE
Auto Flow Control Enable.
Writeable only when AFCE_MODE == Enabled, always readable.  When FIFOs are enabled
and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are
enabled as described in section 5.6 on page 51.
0 = Auto Flow Control Mode disabled
1 = Auto Flow Control Mode enabled
Value Description
0x0 Auto Flow Control Mode disabled
0x1 Auto Flow Control Mode enabled
RW 0x0
4 LoopBack
LoopBack Bit.
This is used to put the UART into a diagnostic mode for test purposes.
If operating in UART mode (SIR_MODE != Enabled OR NOT active, MCR[6] set to zero),
data on the sout line is held high, while serial data output is looped back to the
sin line, internally. In this mode all the interrupts are fully functional. Also,
in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are
disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped
back to the inputs, internally.
If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one),
data on the sir_out_n line is held low, while serial data output is inverted and
looped back to the sir_in line.
Value Description
0x0 Loopback mode disabled
0x1 Loopback mode enabled
RW 0x0
3 OUT2
OUT2.
This is used to directly control the user-designated Output2 (out2_n) output. The
value written to this location is inverted and driven out on out2_n, that is:
0 = out2_n de-asserted (logic 1)
1 = out2_n asserted (logic 0)
Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive
high while the value of this location is internally looped back to an input.
Value Description
0x0 out2_n de-asserted (logic 1)
0x1 out2_n asserted (logic 0)
RW 0x0
2 OUT1
OUT1.
This is used to directly control the user-designated Output1 (out1_n) output. The
value written to this location is inverted and driven out on out1_n, that is:
0 = out1_n de-asserted (logic 1)
1 = out1_n asserted (logic 0)
Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high
while the value of this location is internally looped back to an input.
Value Description
0x0 out1_n de-asserted (logic 1)
0x1 out1_n asserted (logic 0)
RW 0x0
1 RTS
Request to Send. 
This is used to directly control the Request to Send (rts_n) output. The Request
To Send (rts_n) output is used to inform the modem or data set that the UART is
ready to exchange data.
When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal
is set low by programming MCR[1] (RTS) to a high.
In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and
FIFO's enable (FCR[0] set to one), the rts_n output is controlled in the same way,
but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high
when above the threshold).
The rts_n signal will be de-asserted when MCR[1] is set low.
Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive
high while the value of this location is internally looped back to an input.
Value Description
0x0 Request to Send rts_n de-asserted (logic 1)
0x1 Request to Send rts_n asserted (logic 0)
RW 0x0
0 DTR
Data Terminal Ready.
This is used to directly control the Data Terminal Ready (dtr_n) output. The value
written to this location is inverted and driven out on dtr_n, that is:
0 = dtr_n de-asserted (logic 1)
1 = dtr_n asserted (logic 0)
The Data Terminal Ready output is used to inform the modem or data set that the
UART is ready to establish communications. Note that in Loopback mode (MCR[4]
set to one), the dtr_n output is held inactive high while the value of this
location is internally looped back to an input.
Value Description
0x0 Data Terminal Ready dtr_n de-asserted (logic1)
0x1 Data Terminal Ready dtr_n asserted (logic 0)
RW 0x0