sdmam

         Shadow DMA Mode.
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC02094
i_uart_1_uart_address_block 0xFFC02100 0xFFC02194

Size: 32

Offset: 0x94

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_sdmam_31to1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_sdmam_31to1

RO 0x0

sdmam

RW 0x0

sdmam Fields

Bit Name Description Access Reset
31:1 rsvd_sdmam_31to1
Reserved bits [31:1] - Read Only
RO 0x0
0 sdmam
Shadow DMA Mode.
This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove
the burden of having to store the previously written value to the FCR in memory and
having to mask this value so that only the DMA Mode bit gets updated.
This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n
output signals when additional DMA handshaking signals are not selected
(DMA_EXTRA == NO). See section 5.9 on page 54 for details on DMA support.
0 = mode 0
1 = mode 1
Value Description
0 Single DMA Transfer Mode
1 Multiple DMA Transfer Mode
RW 0x0