reg_dramaddrw 

         DRAM Address Width Register
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF80100A8

Size: 32

Offset: 0xA8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_cs_addr_width

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_bank_group_addr_width

RO 0x0

cfg_bank_addr_width

RO 0x0

cfg_row_addr_width

RO 0x0

cfg_col_addr_width

RO 0x0

reg_dramaddrw Fields

Bit Name Description Access Reset
18:16 cfg_cs_addr_width 
iohmc_ctrl_mmr_top_inst.cfg_cs_addr_width[2:0]
Name:DRAM Chip Address Bits
Description:The number of chip select address bits for the memory devices in your memory interface.
RO 0x0
15:14 cfg_bank_group_addr_width 
iohmc_ctrl_mmr_top_inst.cfg_bank_group_addr_width[1:0]
Name:DRAM Bank Group Address Bits
Description:The number of bank group address bits for the memory devices in your memory interface.
RO 0x0
13:10 cfg_bank_addr_width 
iohmc_ctrl_mmr_top_inst.cfg_bank_addr_width[3:0]
Name:DRAM Bank Address Bits
Description:The number of bank address bits for the memory devices in your memory interface.
RO 0x0
9:5 cfg_row_addr_width 
iohmc_ctrl_mmr_top_inst.cfg_row_addr_width[4:0]
Name:DRAM Row Address Bits
Description:The number of row address bits for the memory devices in your memory interface.
RO 0x0
4:0 cfg_col_addr_width 
iohmc_ctrl_mmr_top_inst.cfg_col_addr_width[4:0]
Name:DRAM Column Address Bits
Description:The number of column address bits for the memory devices in your memory interface.
RO 0x0