reg_ctrlcfg9

         
      
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF801004C

Size: 32

Offset: 0x4C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dfx_bypass_en

RW 0x0

reg_ctrlcfg9 Fields

Bit Name Description Access Reset
0 cfg_dfx_bypass_en
iohmc_ctrl_mmr_top_inst.cfg_dfx_bypass_en
Name:DFX Bypass Mode Enable
Description:Used for dft and timing characterization only.
1’b0: Normal functional mode, 1’b1: DFX bypass mode.
RW 0x0