io_pa_ctrl

         HMC clock status indicator

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD12000`	`0xFFD120B8`

Size: 32

Offset: 0xB8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`													`io_pa_reset_n_c` `RW 0x1`	`io_pa_reset_n_b` `RW 0x1`	`io_pa_reset_n_a` `RW 0x1`

io_pa_ctrl Fields

Bit	Name	Description	Access	Reset
2	`io_pa_reset_n_c`	This will allow HPS software to control when it wants to start receiving the IO48 clock.	`RW`	`0x1`
1	`io_pa_reset_n_b`	This will allow HPS software to control when it wants to start receiving the IO48 clock.	`RW`	`0x1`
0	`io_pa_reset_n_a`	This will allow HPS software to control when it wants to start receiving the IO48 clock.	`RW`	`0x1`

Bit

Name

Description

Access

Reset

io_pa_reset_n_c

This will allow HPS software to control when it wants to start receiving the IO48 clock.

RW

0x1

io_pa_reset_n_b

This will allow HPS software to control when it wants to start receiving the IO48 clock.

RW

0x1

io_pa_reset_n_a

This will allow HPS software to control when it wants to start receiving the IO48 clock.

RW

0x1