SMMU_ITOP_PERF_INDEX

         Enables TBU performance interrupts.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA00200C

Size: 32

Offset: 0x200C

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

WAY_IPA2PA_PF

WO 0x0

Reserved

IPA2PA_PF_INDEX

WO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WAY_MTLB_WC

WO 0x0

Reserved

MTLB_WC_INDEX

WO 0x0