tapmodrst 

         The TAPMODRST register is used by software to trigger module resets. Software triggers the assertion of the TAP module reset signal by writing 1 to the TAP bit. The Reset Manager will hold the TAP module reset signal asserted for 1000 clock cycles and then release the TAP module reset. If the TAP module is currently asserted, writing to this register has no effect.

All fields are reset by a por reset. The reset value of all fields is 0.
Module Instance Base Address Register Address
i_rst_mgr_rstmgr 0xFFD11000 0xFFD11040

Size: 32

Offset: 0x40

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

tap

RW 0x0

tapmodrst Fields

Bit Name Description Access Reset
0 tap 
Resets logic located only in the jtag tap domain.
 RW 0x0