ddr_T_main_Scheduler_Ddr4Timing 

         Long timing for DDR4 Bank Group support.
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_ddr_T_main_Scheduler 0xF8000400 0xF8000440

Size: 32

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

RRDL

RW 0x3

WRTORDL

RW 0xC

CCDL

RW 0x7

ddr_T_main_Scheduler_Ddr4Timing Fields

Bit Name Description Access Reset
11:8 RRDL 
Project-Id-Version:  2.11.4
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RW 0x3
7:3 WRTORDL 
Project-Id-Version:  2.11.4
Report-Msgid-Bugs-To: 
POT-Creation-Date: 2015-03-03 12:49+CET
PO-Revision-Date: 2009-01-19 17:46+0100
Last-Translator: ARTERIS <twt@arteris.com>
Language-Team: en_US <twt@arteris.com>
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RW 0xC
2:0 CCDL 
Project-Id-Version:  2.11.4
Report-Msgid-Bugs-To: 
POT-Creation-Date: 2015-03-03 12:49+CET
PO-Revision-Date: 2009-01-19 17:46+0100
Last-Translator: ARTERIS <twt@arteris.com>
Language-Team: en_US <twt@arteris.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
RW 0x7