GDFIFOCFG

         Global DFIFO Configuration Register

Module Instance	Base Address	Register Address
`i_usbotg_0_DWC_otg_intreg`	`0xFFB00000`	`0xFFB0005C`
`i_usbotg_1_DWC_otg_intreg`	`0xFFB40000`	`0xFFB4005C`

Size: 32

Offset: 0x5C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`EPInfoBaseAddr` `RW 0x1F80`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`GDFIFOCfg` `RW 0x2000`

GDFIFOCFG Fields

Bit	Name	Description	Access	Reset
31:16	`EPInfoBaseAddr`	EPInfoBaseAddr This field provides the start address of the EP info controller.	`RW`	`0x1F80`
15:0	`GDFIFOCfg`	GDFIFOCfg This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The value programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The DWC_otg core does not have any corrective logic if the FIFO sizes are programmed incorrectly.	`RW`	`0x2000`

Bit

Name

Description

Access

Reset

31:16

EPInfoBaseAddr

  EPInfoBaseAddr	
	This field provides the start address of the EP info controller.

RW

0x1F80

15:0

GDFIFOCfg

	GDFIFOCfg
	This field is for dynamic programming of the DFIFO Size. This value takes effect
only when the application programs a non zero value to this register. The
value programmed must conform to the guidelines described in 'FIFO RAM
Allocation'. The DWC_otg core does not have any corrective logic
if the FIFO sizes are programmed incorrectly.

RW

0x2000