erase_wait_cnt 

         Wait count value for Erase operation
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA10040

Size: 32

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

value

RW 0x1F40

erase_wait_cnt Fields

Bit Name Description Access Reset
15:0 value 
Number of clock cycles after issue of erase operation before 
                                Cadence NAND Flash Controller polls for status. This values is of
                                relevance for status polling mode of operation and has been
                                provided to minimize redundant polling after issuing a command.
                                After a erase command, the first polling will happen after this many
                                number of cycles have elapsed and then on polling will happen every
                                intmon_cyc_cnt cycles.
                                The default values is equal to the 
                                default value of intmon_cyc_cnt. The controller internally multiplies 
                                the value programmed into this register by 16 to provide a wider 
                                range for polling.
RW 0x1F40