reg_caltiming2

         Calibration Timing 2 Register
      
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF8010084

Size: 32

Offset: 0x84

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

cfg_t_param_wr_to_wr_diff_chip

RO 0x0

cfg_t_param_wr_to_wr

RO 0x0

cfg_t_param_rd_ap_to_valid

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cfg_t_param_rd_ap_to_valid

RO 0x0

cfg_t_param_rd_to_pch

RO 0x0

cfg_t_param_rd_to_wr_diff_bg

RO 0x0

reg_caltiming2 Fields

Bit Name Description Access Reset
29:24 cfg_t_param_wr_to_wr_diff_chip
iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr_diff_chip[5:0]
Name:Wr to Wr  Diff Chip
Description:Write to write command timing on different chips.
RO 0x0
23:18 cfg_t_param_wr_to_wr
iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_to_wr[5:0]
Name:Wr to Wr Same bank
Description:Write to write command timing on same bank.
RO 0x0
17:12 cfg_t_param_rd_ap_to_valid
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_ap_to_valid[5:0]
Name:Rd with Auto Precharge to Valid Cmd
Description:Read command with autoprecharge to data valid timing.
RO 0x0
11:6 cfg_t_param_rd_to_pch
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_pch[5:0]
Name:Rd to Precharge
Description:Read to precharge command timing.
RO 0x0
5:0 cfg_t_param_rd_to_wr_diff_bg
iohmc_ctrl_mmr_top_inst.cfg_t_param_rd_to_wr_diff_bg[5:0]
Name:Rd to Wr Diff Bank Group
Description:Read to write command timing on different bank groups, DDR4 only.
RO 0x0