ddr_scheduler_fpga2sdram1_axi32_I_main_QosGenerator Address Map

Module Instance Base Address End Address
soc_ddr_scheduler_inst_0_fpga2sdram1_axi32_I_main_QosGenerator 0xF8022300 0xF802237F
Register Offset Width Access Reset Value Description
fpga2sdram1_axi32_I_main_QosGenerator_Id_CoreId 0x0 32 RO 0x16344504
FPGA2SDRAM1 AXI-32 QoS Generator Core ID Register
fpga2sdram1_axi32_I_main_QosGenerator_Id_RevisionId 0x4 32 RO 0x00014800
FPGA2SDRAM1 AXI-32 QoS Generator Revision ID Register
fpga2sdram1_axi32_I_main_QosGenerator_Priority 0x8 32 RW 0x80000200
FPGA2SDRAM1 AXI-32 QoS Generator Priority Register
fpga2sdram1_axi32_I_main_QosGenerator_Mode 0xC 32 RW 0x00000003
FPGA2SDRAM1 AXI-32 QoS Generator Mode Register
fpga2sdram1_axi32_I_main_QosGenerator_Bandwidth 0x10 32 RW 0x00000280
FPGA2SDRAM1 AXI-32 QoS Generator Bandwidth Register
fpga2sdram1_axi32_I_main_QosGenerator_Saturation 0x14 32 RW 0x00000008
FPGA2SDRAM1 AXI-32 QoS Generator Saturation Value Register
fpga2sdram1_axi32_I_main_QosGenerator_ExtControl 0x18 32 RW 0x00000000
External inputs control.