GAHBCFG

RESERVED

Invert Descriptor Endianess (InvDescEndianess)
1'b0: Descriptor Endianness is same as AHB Master Endianness
1'b1: Descriptor Endianness is Little Endian if AHB Master Endianness is Big Endian. 
Descriptor Endianness is Big Endian if AHB Master Endianness is Little Endian. 

AHB Single Support (AHBSingle)
This bit when programmed supports Single transfers for the remaining data in a 
transfer when the DWC_otg core is operating in DMA mode. 
1'b0: The remaining data in the transfer is sent using INCR burst size.  
1'b1: The remaining data in the transfer is sent using Single 
      burst size. 
Note: if this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR 
burst type. Enable this feature when the AHB Slave connected to the DWC_otg core does 
not support INCR burst (and when Split, and Retry transactions are not being used 
in the bus).

Notify All Dma Write Transactions (NotiAllDmaWrit)
This bit is programmed to enable the System DMA Done functionality for all
the DMA write Transactions corresponding to the Channel/Endpoint. This bit
is valid only when GAHBCFG.RemMemSupp is set to 1.
 GAHBCFG.NotiAllDmaWrit = 1
- HSOTG core asserts int_dma_req for all the DMA write transactions on
the AHB interface along with int_dma_done, chep_last_transact and
chep_number signal informations. The core waits for sys_dma_done
signal for all the DMA write transactions in order to complete the transfer
of a particular Channel/Endpoint.
 GAHBCFG.NotiAllDmaWrit = 0
- HSOTG core asserts int_dma_req signal only for the last transaction of
DMA write transfer corresponding to a particular Channel/Endpoint.
Similarly, the core waits for sys_dma_done signal only for that
transaction of DMA write to complete the transfer of a particular
Channel/Endpoint.

Remote Memory Support (RemMemSupp)
This bit is programmed to enable the functionality to wait for the system DMA
Done Signal for the DMA Write Transfers.
 GAHBCFG.RemMemSupp=1
- The int_dma_req output signal is asserted when HSOTG DMA starts
write transfer to the external memory. When the core is done with the
Transfers it asserts int_dma_done signal to flag the completion of DMA
writes from HSOTG. The core then waits for sys_dma_done signal from
the system to proceed further and complete the Data Transfer
corresponding to a particular Channel/Endpoint.
 GAHBCFG.RemMemSupp=0
- The int_dma_req and int_dma_done signals are not asserted and the
core proceeds with the assertion of the XferComp interrupt as soon as
the DMA write transfer is done at the HSOTG Core Boundary and it
doesn't wait for the sys_dma_done signal to complete the DATA transfers

Mode:Host only
Periodic TxFIFO Empty Level (PTxFEmpLvl)
Indicates when the Periodic TxFIFO Empty Interrupt bit in the
Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This
bit is used only in Slave mode.
 1'b0: GINTSTS.PTxFEmp interrupt indicates that the
Periodic TxFIFO is half empty
 1'b1: GINTSTS.PTxFEmp interrupt indicates that the
Periodic TxFIFO is completely empty

Mode:Host and device
Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
This bit is used only in Slave mode.
In host mode and with Shared FIFO with device mode, this bit
indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.
With dedicated FIFO in device mode, this bit indicates when IN
endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is
triggered.
Host mode and with Shared FIFO with device mode:-
 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
Periodic TxFIFO is half empty
 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
Periodic TxFIFO is completely empty
Dedicated FIFO in device mode :-
 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN
Endpoint TxFIFO is half empty
 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN
Endpoint TxFIFO is completely empty

RESERVED

Mode:Host and device
DMA Enable (DMAEn)
 1'b0: Core operates in Slave mode
 1'b1: Core operates in a DMA mode
This bit is always 0 when Slave-Only mode has been selected

Mode:Host and device
Burst Length/Type (HBstLen)
This field is used in both External and Internal DMA modes. In
External DMA mode, these bits appear on dma_burst[3:0] ports,
which can be used by an external wrapper to interface the
External DMA Controller interface to Synopsys DW_ahb_dmac
or ARM PrimeCell.
External DMA Mode defines the DMA burst length in terms of
32-bit words:
 4'b0000: 1 word
 4'b0001: 4 words
 4'b0010: 8 words
 4'b0011: 16 words
 4'b0100: 32 words
 4'b0101: 64 words
 4'b0110: 128 words
 4'b0111: 256 words
 Others: Reserved
Internal DMA ModeAHB Master burst type:
 4'b0000 Single
 4'b0001 INCR
 4'b0011 INCR4
 4'b0101 INCR8
 4'b0111 INCR16
 Others: Reserved

Mode:Host and device
Global Interrupt Mask (GlblIntrMsk)
The application uses this bit to mask or unmask the interrupt line
assertion to itself. Irrespective of this bit's setting, the interrupt
status registers are updated by the core.
 1'b0: Mask the interrupt assertion to the application.
 1'b1: Unmask the interrupt assertion to the application.