fcr

         FIFO Control Register

Module Instance	Base Address	Register Address
`i_uart_0_uart_address_block`	`0xFFC02000`	`0xFFC02008`
`i_uart_1_uart_address_block`	`0xFFC02100`	`0xFFC02108`

Size: 32

Offset: 0x8

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`rt` `WO 0x0`		`tet` `WO 0x0`		`dmam` `WO 0x0`	`xfifor` `WO 0x0`	`rfifor` `WO 0x0`	`fifoe` `WO 0x0`

fcr Fields

Bit

Name

Description

Access

Reset

7:6

rt

Bits[7:6], RCVR Trigger (or RT):.
This is used to select the trigger level in the receiver FIFO at which the
Received Data Available Interrupt will be generated. In auto flow control mode
it is used to determine when the rts_n signal will be de-asserted. It also
determines when the dma_rx_req_n signal will be asserted when in certain modes
of operation. See section 5.9 on page 56 for details on DMA support. The
following trigger levels are supported:
00 = 1 character in the FIFO
01 = FIFO 1/4 full
10 = FIFO 1/2 full
11 = FIFO 2 less than full

Value	Description
0	1 character in FIFO
1	FIFO 1/4 full
2	FIFO 1/2 full
3	FIFO 2 less than full

WO

0x0

5:4

tet

Bits[5:4], TX Empty Trigger (or TET):
Writes will have no effect when THRE_MODE_USER == Disabled. This is used to select
the empty threshold level at which the THRE Interrupts will be generated when the
mode is active. It also determines when the dma_tx_req_n signal will be asserted when
in certain modes of operation. See section 5.9 on page 56 for details on DMA support.
The following trigger levels are supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO 1/4 full
11 = FIFO full

Value	Description
0	FIFO empty
1	2 characters in FIFO
2	FIFO 1/4 full
3	FIFO 1/2 full

WO

0x0

dmam

Bit[3], DMA Mode (or DMAM):
This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n
output signals when additional DMA handshaking signals are not selected
(DMA_EXTRA == NO). See section 5.9 on page 56 for details on DMA support.
0 = mode 0
1 = mode 1

Value	Description
0	Mode 0
1	Mode 1

WO

0x0

xfifor

Bit[2], XMIT FIFO Reset (or XFIFOR):
This resets the control portion of the transmit FIFO and treats the FIFO as empty.
This will also de-assert the DMA TX request and single signals when additional
DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is
'self-clearing' and it is not necessary to clear this bit.

Value	Description
1	Transmit FIFO reset

WO

0x0

rfifor

Bit[1], RCVR FIFO Reset (or RFIFOR):
This resets the control portion of the receive FIFO and treats the FIFO as empty.
This will also de-assert the DMA RX request and single signals when additional
DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is
'self-clearing' and it is not necessary to clear this bit.

Value	Description
1	Receive FIFO reset

WO

0x0

fifoe

Bit[0], FIFO Enable (or FIFOE):
This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the
value of this bit is changed both the XMIT and RCVR controller portion of FIFO's
will be reset.

Value	Description
0	FIFO disabled
1	FIFO enabled

WO

0x0