firewall_ddr_scheduler_mpfe_scr Address Map

DDR Scheduler Security Control Registers (SCR)
Module Instance Base Address End Address
soc_noc_fw_mpfe_csr_inst_0_mpfe_scr 0xF8020000 0xF80200FF
Register Offset Width Access Reset Value Description
hmc_register 0x0 32 RW 0x00000000
Per-Master Security bit for hmc_register
hmc_adaptor_register 0x4 32 RW 0x00000000
Per-Master Security bit for hmc_adaptor_register
fpga2sdram_sidebandmgr 0x18 32 RW 0x00000000
Per-Master Security bit for fpga2sdram_sidebandmgr
noc_probes 0x14 32 RW 0x00000000
Per-Master Security bit for noc_probes_register
noc_scheduler_csr 0x8 32 RW 0x00000000
Per-Master Security bit for ddr_scheduler_register
noc_qos 0x10 32 RW 0x00000000
Per-Master Security bit for noc_qos_register