acc_clks 

         Timing parameter from read enable going low to capture read data
Module Instance Base Address Register Address
sdm_i_nand_config 0xFFA10000 0xFFA10130

Size: 32

Offset: 0x130

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

value

RW 0x0

acc_clks Fields

Bit Name Description Access Reset
3:0 value 
Signifies the number of bus interface clk_x clock cycles, controller
                           should wait from read enable going low to sending out a strobe of clk_x for 
                           capturing of incoming data.
RW 0x0